Andrew Waterman eb0b5ec61e Remove stats CSR

2016-04-27 00:16:21 -07:00

..

amoalu.scala

Extend AMOALU to support RV32

2016-03-10 17:32:23 -08:00

broadcast.scala

fix BroadcastHub allocation and routing

2016-04-05 16:21:18 -07:00

cache.scala

don't add pending reads if data is already available

2016-04-06 15:43:21 -07:00

coherence.scala

fix more Chisel3 deprecations

2016-01-14 14:55:45 -08:00

consts.scala

Let isRead be true for store-conditional

2015-09-25 15:28:02 -07:00

converters.scala

Simplify TileLink Narrower

2016-04-26 16:44:54 -07:00

directory.scala

First pages commit

2015-04-29 13:18:26 -07:00

dma.scala

make sure CSR width is parameterizable

2016-02-02 12:49:58 -08:00

ecc.scala

Chisel3 compatibility: use >>Int instead of >>UInt

2015-08-04 13:15:17 -07:00

htif.scala

Remove stats CSR

2016-04-27 00:16:21 -07:00

interconnect.scala

avoid logical to physical header conversion overflow

2016-04-22 17:47:34 +01:00

metadata.scala

Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.

2016-03-10 17:14:34 -08:00

network.scala

Improve simulation speed of BasicCrossbar

2016-04-01 13:28:11 -07:00

package.scala

First pages commit

2015-04-29 13:18:26 -07:00

rom.scala

Replace NastiROM with ROMSlave, which uses TileLink

2016-04-27 00:15:30 -07:00

rtc.scala

switch RTC to use TileLink instead of AXI

2016-03-28 12:23:16 -07:00

scr.scala

changes to match junctions no-mmio-base

2016-04-21 15:35:37 -07:00

tilelink.scala

use manager_id instead of client_id in GrantFromSrc and FinishToDst

2016-04-07 11:20:16 -07:00

uncore.scala

fix BroadcastHub allocation and routing

2016-04-05 16:21:18 -07:00

util.scala

Chisel3 compatibility fix

2016-03-10 17:32:23 -08:00