.. |
arbiter.scala
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Don't rely on tag value for nacks
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2016-05-24 15:05:41 -07:00 |
breakpoint.scala
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Refactor breakpoints and support range comparison (currently disabled)
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2016-06-10 19:55:58 -07:00 |
btb.scala
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Remove dead code from BTB
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2016-04-27 00:28:12 -07:00 |
consts.scala
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WIP on priv spec v1.9
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2016-03-02 23:29:58 -08:00 |
csr.scala
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Mask interrupts during single-step
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2016-06-23 00:01:06 -07:00 |
dcache.scala
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Merge sptbr and sasid
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2016-06-17 18:29:05 -07:00 |
decode.scala
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Use Seq, not Iterable, when traversal order matters
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2015-07-29 00:24:58 -07:00 |
dma.scala
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Cope with changes to AddrMap
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2016-06-03 13:50:29 -07:00 |
dpath_alu.scala
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Improve ALU QoR
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2016-01-20 17:42:31 -08:00 |
fpu.scala
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remove implicit modulo addressing in FPU (#44)
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2016-06-09 11:33:33 -07:00 |
frontend.scala
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Always verify BTB result; don't bother flushing it
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2016-06-23 00:01:06 -07:00 |
icache.scala
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Support larger I$ sets when VM is disabled
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2016-05-24 15:44:59 -07:00 |
idecode.scala
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First stab at debug interrupts
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2016-06-01 16:57:10 -07:00 |
instructions.scala
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Merge sptbr and sasid
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2016-06-17 18:29:05 -07:00 |
multiplier.scala
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Remove unnecessary muxes in RV32 MulDiv
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2016-05-25 14:27:02 -07:00 |
nbdcache.scala
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Merge sptbr and sasid
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2016-06-17 18:29:05 -07:00 |
package.scala
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make mtvec configurable and writeable
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2016-01-29 14:51:56 -08:00 |
ptw.scala
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make sure UseAtomics is on when PTW is being used
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2016-06-22 16:09:45 -07:00 |
rocc.scala
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set invalidate_lr in other rocc examples (#47)
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2016-06-14 16:59:37 -07:00 |
rocket.scala
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Don't take interrupts on instructions in branch shadow
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2016-06-28 12:47:49 -07:00 |
tile.scala
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change Tile interface to allow arbitrary number of cached and uncached channels
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2016-06-20 09:55:30 -07:00 |
tlb.scala
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Merge sptbr and sasid
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2016-06-17 18:29:05 -07:00 |
util.scala
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Get rid of unused implicit conversion
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2016-06-01 19:30:41 -07:00 |