Andrew Waterman 84fd45fd77 Pass TLB flush signal to I$ explicitly

2016-04-22 15:20:17 -07:00

..

arbiter.scala

Separate I$ and D$ interface signals that span clock cycles

2016-04-01 19:30:39 -07:00

btb.scala

Remove vestigial BTB enable option

2016-04-01 15:14:34 -07:00

consts.scala

WIP on priv spec v1.9

2016-03-02 23:29:58 -08:00

csr.scala

use address map instead of MMIOBase to find size of memory

2016-04-21 18:44:39 -07:00

decode.scala

Use Seq, not Iterable, when traversal order matters

2015-07-29 00:24:58 -07:00

dma.scala

use address map instead of MMIOBase to find size of memory

2016-04-21 18:44:39 -07:00

dpath_alu.scala

Improve ALU QoR

2016-01-20 17:42:31 -08:00

fpu.scala

Added Field[Int] to SFMALatency/DFMALatency params

2016-04-06 14:50:57 -07:00

frontend.scala

Pass TLB flush signal to I$ explicitly

2016-04-22 15:20:17 -07:00

icache.scala

Separate I$ and D$ interface signals that span clock cycles

2016-04-01 19:30:39 -07:00

idecode.scala

Add RV32 support

2016-03-10 17:32:00 -08:00

instructions.scala

WIP on priv spec v1.9

2016-03-02 23:29:58 -08:00

multiplier.scala

fix more Chisel3 deprecations

2016-01-14 14:46:31 -08:00

nbdcache.scala

use address map instead of MMIOBase to find size of memory

2016-04-21 18:44:39 -07:00

package.scala

make mtvec configurable and writeable

2016-01-29 14:51:56 -08:00

ptw.scala

Separate I$ and D$ interface signals that span clock cycles

2016-04-01 19:30:39 -07:00

rocc.scala

WIP on priv spec v1.9

2016-03-02 23:29:58 -08:00

rocket.scala

Pass TLB flush signal to I$ explicitly

2016-04-22 15:20:17 -07:00

tile.scala

Use correct kind of TileLink arbiter

2016-03-28 22:53:47 -07:00

tlb.scala

Fix Chisel3 build for UseVM=false

2016-03-30 22:48:31 -07:00

util.scala

Fix Chisel3 build for XLen=32

2016-03-30 22:48:51 -07:00