| .. |
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arbiter.scala
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Separate I$ and D$ interface signals that span clock cycles
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2016-04-01 19:30:39 -07:00 |
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btb.scala
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Remove vestigial BTB enable option
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2016-04-01 15:14:34 -07:00 |
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consts.scala
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WIP on priv spec v1.9
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2016-03-02 23:29:58 -08:00 |
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csr.scala
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use address map instead of MMIOBase to find size of memory
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2016-04-21 18:44:39 -07:00 |
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decode.scala
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Use Seq, not Iterable, when traversal order matters
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2015-07-29 00:24:58 -07:00 |
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dma.scala
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use address map instead of MMIOBase to find size of memory
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2016-04-21 18:44:39 -07:00 |
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dpath_alu.scala
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Improve ALU QoR
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2016-01-20 17:42:31 -08:00 |
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fpu.scala
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Added Field[Int] to SFMALatency/DFMALatency params
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2016-04-06 14:50:57 -07:00 |
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frontend.scala
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Pass TLB flush signal to I$ explicitly
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2016-04-22 15:20:17 -07:00 |
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icache.scala
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Separate I$ and D$ interface signals that span clock cycles
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2016-04-01 19:30:39 -07:00 |
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idecode.scala
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Add RV32 support
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2016-03-10 17:32:00 -08:00 |
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instructions.scala
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WIP on priv spec v1.9
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2016-03-02 23:29:58 -08:00 |
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multiplier.scala
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fix more Chisel3 deprecations
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2016-01-14 14:46:31 -08:00 |
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nbdcache.scala
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use address map instead of MMIOBase to find size of memory
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2016-04-21 18:44:39 -07:00 |
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package.scala
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make mtvec configurable and writeable
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2016-01-29 14:51:56 -08:00 |
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ptw.scala
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Separate I$ and D$ interface signals that span clock cycles
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2016-04-01 19:30:39 -07:00 |
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rocc.scala
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WIP on priv spec v1.9
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2016-03-02 23:29:58 -08:00 |
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rocket.scala
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Pass TLB flush signal to I$ explicitly
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2016-04-22 15:20:17 -07:00 |
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tile.scala
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Use correct kind of TileLink arbiter
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2016-03-28 22:53:47 -07:00 |
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tlb.scala
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Fix Chisel3 build for UseVM=false
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2016-03-30 22:48:31 -07:00 |
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util.scala
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Fix Chisel3 build for XLen=32
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2016-03-30 22:48:51 -07:00 |
