| .. |
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AddressDecoder.scala
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tilelink2 AddressDecoder: validate output of optimization
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2016-09-16 16:09:00 -07:00 |
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Buffer.scala
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tilelink2: add a clock crossing adapter
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2016-09-13 18:33:56 -07:00 |
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Bundles.scala
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Crossing.scala
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Edges.scala
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tilelink2: differentiate fast/safe address lookup cases
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2016-09-17 17:04:18 -07:00 |
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Example.scala
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Merge remote-tracking branch 'origin/master' into black_box_regs
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2016-09-09 13:12:52 -07:00 |
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Fragmenter.scala
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tilelink2: differentiate fast/safe address lookup cases
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2016-09-17 17:04:18 -07:00 |
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Fuzzer.scala
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tilelink2: Fuzzer should check address validity before injection
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2016-09-17 17:07:21 -07:00 |
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HintHandler.scala
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tilelink2: differentiate fast/safe address lookup cases
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2016-09-17 17:04:18 -07:00 |
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IntNodes.scala
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tilelink2: track interrupt connectivity like in TL2
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2016-09-17 14:43:48 -07:00 |
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LazyModule.scala
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tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
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2016-09-08 23:06:59 -07:00 |
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Legacy.scala
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testconfigs: disable atomics until AtomicAbsorber finished
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2016-09-15 21:28:56 -07:00 |
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Monitor.scala
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tilelink2: differentiate fast/safe address lookup cases
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2016-09-17 17:04:18 -07:00 |
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Nodes.scala
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tilelink2: Nodes can now mix context into parameters
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2016-09-16 17:28:47 -07:00 |
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package.scala
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tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec
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2016-09-08 21:34:20 -07:00 |
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Parameters.scala
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tilelink2: differentiate fast/safe address lookup cases
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2016-09-17 17:04:18 -07:00 |
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RAMModel.scala
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tilelink2: differentiate fast/safe address lookup cases
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2016-09-17 17:04:18 -07:00 |
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RegField.scala
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RegField: separate UInt=>bytes and bytes=>regs
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2016-09-16 14:24:28 -07:00 |
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RegisterCrossing.scala
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Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
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2016-09-14 17:50:17 -07:00 |
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RegisterRouter.scala
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tilelink2: remove 'strided'; !contiguous is clearer
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2016-09-17 16:14:25 -07:00 |
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RegisterRouterTest.scala
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tilelink2 RegisterRouterTest: work around firrtl warning
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2016-09-16 16:09:00 -07:00 |
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RegMapper.scala
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tilelink2 RegisterRouter: support undefZero
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2016-09-16 16:09:00 -07:00 |
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SRAM.scala
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SRAM: optionally (default: true) executable
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2016-09-17 00:19:37 -07:00 |
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TLNodes.scala
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tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters
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2016-09-16 17:28:47 -07:00 |
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WidthWidget.scala
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Xbar.scala
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tilelink2: minimize Xbar decode logic
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2016-09-17 16:14:25 -07:00 |
