182 lines
7.6 KiB
Scala
182 lines
7.6 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import chisel3._
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import chisel3.util._
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// A bus agnostic register interface to a register-based device
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case class RegMapperParams(indexBits: Int, maskBits: Int, extraBits: Int)
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class RegMapperInput(params: RegMapperParams) extends GenericParameterizedBundle(params)
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{
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val read = Bool()
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val index = UInt(width = params.indexBits)
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val data = UInt(width = params.maskBits*8)
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val mask = UInt(width = params.maskBits)
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val extra = UInt(width = params.extraBits)
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}
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class RegMapperOutput(params: RegMapperParams) extends GenericParameterizedBundle(params)
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{
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val read = Bool()
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val data = UInt(width = params.maskBits*8)
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val extra = UInt(width = params.extraBits)
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}
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object RegMapper
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{
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// Create a generic register-based device
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def apply(bytes: Int, concurrency: Option[Int], undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*) = {
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val regmap = mapping.toList.filter(!_._2.isEmpty)
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require (!regmap.isEmpty)
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// Ensure no register appears twice
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regmap.combinations(2).foreach { case Seq((reg1, _), (reg2, _)) =>
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require (reg1 != reg2)
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}
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// Don't be an asshole...
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regmap.foreach { reg => require (reg._1 >= 0) }
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// Make sure registers fit
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val inParams = in.bits.params
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val inBits = inParams.indexBits
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assert (regmap.map(_._1).max < (1 << inBits))
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val out = Wire(Irrevocable(new RegMapperOutput(inParams)))
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val front = Wire(Irrevocable(new RegMapperInput(inParams)))
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front.bits := in.bits
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// Must this device pipeline the control channel?
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val pipelined = regmap.map(_._2.map(_.pipelined)).flatten.reduce(_ || _)
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val depth = concurrency.getOrElse(if (pipelined) 1 else 0)
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require (depth >= 0)
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require (!pipelined || depth > 0)
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val back = if (depth > 0) Queue(front, depth, pipe = depth == 1) else front
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// Convert to and from Bits
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def toBits(x: Int, tail: List[Boolean] = List.empty): List[Boolean] =
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if (x == 0) tail.reverse else toBits(x >> 1, ((x & 1) == 1) :: tail)
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def ofBits(bits: List[Boolean]) = bits.foldRight(0){ case (x,y) => (if (x) 1 else 0) | y << 1 }
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// Find the minimal mask that can decide the register map
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val mask = AddressDecoder(regmap.map(_._1))
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val maskMatch = ~UInt(mask, width = inBits)
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val maskFilter = toBits(mask)
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val maskBits = maskFilter.filter(x => x).size
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// Calculate size and indexes into the register map
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val regSize = 1 << maskBits
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def regIndexI(x: Int) = ofBits((maskFilter zip toBits(x)).filter(_._1).map(_._2))
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def regIndexU(x: UInt) = if (maskBits == 0) UInt(0) else
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Cat((maskFilter zip x.toBools).filter(_._1).map(_._2).reverse)
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// Protection flag for undefined registers
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val iRightReg = Array.fill(regSize) { Bool(true) }
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val oRightReg = Array.fill(regSize) { Bool(true) }
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// Flatten the regmap into (RegIndex:Int, Offset:Int, field:RegField)
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val flat = regmap.map { case (reg, fields) =>
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val offsets = fields.scanLeft(0)(_ + _.width).init
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val index = regIndexI(reg)
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val uint = UInt(reg, width = inBits)
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if (undefZero) {
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iRightReg(index) = ((front.bits.index ^ uint) & maskMatch) === UInt(0)
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oRightReg(index) = ((back .bits.index ^ uint) & maskMatch) === UInt(0)
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}
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// println("mapping 0x%x -> 0x%x for 0x%x/%d".format(reg, index, mask, maskBits))
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(offsets zip fields) map { case (o, f) => (index, o, f) }
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}.flatten
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// Forward declaration of all flow control signals
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val rivalid = Wire(Vec(flat.size, Bool()))
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val wivalid = Wire(Vec(flat.size, Bool()))
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val riready = Wire(Vec(flat.size, Bool()))
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val wiready = Wire(Vec(flat.size, Bool()))
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val rovalid = Wire(Vec(flat.size, Bool()))
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val wovalid = Wire(Vec(flat.size, Bool()))
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val roready = Wire(Vec(flat.size, Bool()))
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val woready = Wire(Vec(flat.size, Bool()))
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// Per-register list of all control signals needed for data to flow
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val rifire = Array.tabulate(regSize) { i => Seq(Bool(true)) }
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val wifire = Array.tabulate(regSize) { i => Seq(Bool(true)) }
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val rofire = Array.tabulate(regSize) { i => Seq(Bool(true)) }
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val wofire = Array.tabulate(regSize) { i => Seq(Bool(true)) }
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// The output values for each register
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val dataOut = Array.tabulate(regSize) { _ => UInt(0) }
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// Which bits are touched?
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val frontMask = FillInterleaved(8, front.bits.mask)
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val backMask = FillInterleaved(8, back .bits.mask)
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// Connect the fields
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for (i <- 0 until flat.size) {
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val (reg, low, field) = flat(i)
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val high = low + field.width - 1
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// Confirm that no register is too big
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require (high < 8*bytes)
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val rimask = frontMask(high, low).orR()
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val wimask = frontMask(high, low).andR()
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val romask = backMask(high, low).orR()
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val womask = backMask(high, low).andR()
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val data = if (field.write.combinational) back.bits.data else front.bits.data
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val (f_riready, f_rovalid, f_data) = field.read.fn(rivalid(i) && rimask, roready(i) && romask)
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val (f_wiready, f_wovalid) = field.write.fn(wivalid(i) && wimask, woready(i) && womask, data(high, low))
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riready(i) := f_riready || !rimask
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wiready(i) := f_wiready || !wimask
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rovalid(i) := f_rovalid || !romask
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wovalid(i) := f_wovalid || !womask
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rifire(reg) = riready(i) +: rifire(reg)
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wifire(reg) = wiready(i) +: wifire(reg)
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rofire(reg) = rovalid(i) +: rofire(reg)
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wofire(reg) = wovalid(i) +: wofire(reg)
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dataOut(reg) = dataOut(reg) | ((f_data << low) & (~UInt(0, width = high+1)))
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}
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// Is the selected register ready?
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val rifireMux = Vec(rifire.zipWithIndex.map { case (seq, i) => !iRightReg(i) || seq.reduce(_ && _)})
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val wifireMux = Vec(wifire.zipWithIndex.map { case (seq, i) => !iRightReg(i) || seq.reduce(_ && _)})
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val rofireMux = Vec(rofire.zipWithIndex.map { case (seq, i) => !oRightReg(i) || seq.reduce(_ && _)})
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val wofireMux = Vec(wofire.zipWithIndex.map { case (seq, i) => !oRightReg(i) || seq.reduce(_ && _)})
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val iindex = regIndexU(front.bits.index)
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val oindex = regIndexU(back .bits.index)
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val iready = Mux(front.bits.read, rifireMux(iindex), wifireMux(iindex))
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val oready = Mux(back .bits.read, rofireMux(oindex), wofireMux(oindex))
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// Connect the pipeline
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in.ready := front.ready && iready
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front.valid := in.valid && iready
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back.ready := out.ready && oready
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out.valid := back.valid && oready
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// Which register is touched?
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val frontSel = UIntToOH(iindex) & Cat(iRightReg.reverse)
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val backSel = UIntToOH(oindex) & Cat(oRightReg.reverse)
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// Include the per-register one-hot selected criteria
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for (reg <- 0 until regSize) {
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rifire(reg) = (in.valid && front.ready && front.bits.read && frontSel(reg)) +: rifire(reg)
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wifire(reg) = (in.valid && front.ready && !front.bits.read && frontSel(reg)) +: wifire(reg)
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rofire(reg) = (back.valid && out.ready && back .bits.read && backSel (reg)) +: rofire(reg)
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wofire(reg) = (back.valid && out.ready && !back .bits.read && backSel (reg)) +: wofire(reg)
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}
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// Connect the field's ivalid and oready
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for (i <- 0 until flat.size) {
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val (reg, _, _ ) = flat(i)
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rivalid(i) := rifire(reg).filter(_ ne riready(i)).reduce(_ && _)
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wivalid(i) := wifire(reg).filter(_ ne wiready(i)).reduce(_ && _)
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roready(i) := rofire(reg).filter(_ ne rovalid(i)).reduce(_ && _)
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woready(i) := wofire(reg).filter(_ ne wovalid(i)).reduce(_ && _)
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}
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out.bits.read := back.bits.read
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out.bits.data := Mux(Vec(oRightReg)(oindex), Vec(dataOut)(oindex), UInt(0))
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out.bits.extra := back.bits.extra
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out
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}
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}
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