137 lines
6.2 KiB
Scala
137 lines
6.2 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import cde.Parameters
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import uncore.tilelink._
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import uncore.constants._
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// Instantiate 'val p' before HasTileLinkParameters tries to use it
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abstract class LegacyLazyModuleImp(module: LazyModule)(implicit val p: Parameters)
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extends LazyModuleImp(module) with HasTileLinkParameters
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class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkParameters
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{
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// TL legacy clients don't support anything fancy
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val node = TLClientNode(TLClientParameters(
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sourceId = IdRange(0, 1 << tlClientXactIdBits)))
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lazy val module = new LegacyLazyModuleImp(this) {
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val io = new Bundle {
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val legacy = new ClientUncachedTileLinkIO()(p).flip
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val out = node.bundleOut
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}
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// TL legacy is dumb. All managers must support it's accesses.
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val edge = node.edgesOut(0)
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require (edge.manager.beatBytes == tlDataBytes)
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edge.manager.managers.foreach { m =>
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// If a slave supports read at all, it must support all TL Legacy requires
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if (m.supportsGet) {
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require (m.supportsGet.contains(TransferSizes(tlDataBytes)))
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require (m.supportsGet.contains(TransferSizes(tlDataBeats * tlDataBytes)))
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}
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// Likewise, any put support must mean full put support
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if (m.supportsPutPartial) {
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require (m.supportsPutPartial.contains(TransferSizes(tlDataBytes)))
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require (m.supportsPutPartial.contains(TransferSizes(tlDataBeats * tlDataBytes)))
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}
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// Any atomic support => must support 32-bit up to beat size of all types
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if (m.supportsArithmetic || m.supportsLogical) {
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require (m.supportsArithmetic.contains(TransferSizes(4, tlDataBytes)))
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require (m.supportsLogical .contains(TransferSizes(4, tlDataBytes)))
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}
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// We straight-up require hints
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require (edge.manager.allSupportHint)
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}
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// TL legacy will not generate PutFull
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// During conversion from TL Legacy, we won't support Acquire
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// Must be able to fit TL2 sink_id into TL legacy
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require ((1 << tlManagerXactIdBits) >= edge.manager.endSinkId || !edge.manager.anySupportAcquire)
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val out = io.out(0)
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out.a.valid := io.legacy.acquire.valid
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out.d.ready := io.legacy.grant .ready
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io.legacy.acquire.ready := out.a.ready
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io.legacy.grant .valid := out.d.valid
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val source = io.legacy.acquire.bits.client_xact_id
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val data = io.legacy.acquire.bits.data
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val wmask = io.legacy.acquire.bits.wmask()
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val address = io.legacy.acquire.bits.full_addr()
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val beat = UInt(log2Ceil(tlDataBytes))
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val block = UInt(log2Ceil(tlDataBytes*tlDataBeats))
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// Only create atomic messages if TL2 managers support them
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val atomics = if (edge.manager.anySupportLogical) {
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MuxLookup(io.legacy.acquire.bits.op_code(), Wire(new TLBundleA(edge.bundle)), Array(
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MemoryOpConstants.M_XA_SWAP -> edge.Logical(source, address, beat, data, TLAtomics.SWAP)._2,
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MemoryOpConstants.M_XA_XOR -> edge.Logical(source, address, beat, data, TLAtomics.XOR) ._2,
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MemoryOpConstants.M_XA_OR -> edge.Logical(source, address, beat, data, TLAtomics.OR) ._2,
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MemoryOpConstants.M_XA_AND -> edge.Logical(source, address, beat, data, TLAtomics.AND) ._2,
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MemoryOpConstants.M_XA_ADD -> edge.Arithmetic(source, address, beat, data, TLAtomics.ADD)._2,
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MemoryOpConstants.M_XA_MIN -> edge.Arithmetic(source, address, beat, data, TLAtomics.MIN)._2,
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MemoryOpConstants.M_XA_MAX -> edge.Arithmetic(source, address, beat, data, TLAtomics.MAX)._2,
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MemoryOpConstants.M_XA_MINU -> edge.Arithmetic(source, address, beat, data, TLAtomics.MINU)._2,
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MemoryOpConstants.M_XA_MAXU -> edge.Arithmetic(source, address, beat, data, TLAtomics.MAXU)._2))
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} else {
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// If no managers support atomics, assert fail if TL1 asks for them
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assert (!io.legacy.acquire.valid || io.legacy.acquire.bits.a_type =/= Acquire.putAtomicType)
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Wire(new TLBundleA(edge.bundle))
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}
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out.a.bits := MuxLookup(io.legacy.acquire.bits.a_type, Wire(new TLBundleA(edge.bundle)), Array(
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Acquire.getType -> edge.Get (source, address, beat) ._2,
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Acquire.getBlockType -> edge.Get (source, address, block)._2,
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Acquire.putType -> edge.Put (source, address, beat, data, wmask)._2,
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Acquire.putBlockType -> edge.Put (source, address, block, data, wmask)._2,
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Acquire.getPrefetchType -> edge.Hint(source, address, block, UInt(0))._2,
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Acquire.putPrefetchType -> edge.Hint(source, address, block, UInt(1))._2,
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Acquire.putAtomicType -> atomics))
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val beatMask = UInt(tlDataBytes-1)
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val blockMask = UInt(tlDataBytes*tlDataBeats-1)
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val addressMask = MuxLookup(io.legacy.acquire.bits.a_type, beatMask, Array(
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Acquire.getType -> beatMask,
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Acquire.getBlockType -> blockMask,
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Acquire.putType -> beatMask,
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Acquire.putBlockType -> blockMask,
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Acquire.getPrefetchType -> blockMask,
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Acquire.putPrefetchType -> blockMask,
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Acquire.putAtomicType -> beatMask))
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// Get rid of some unneeded muxes
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out.a.bits.source := source
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out.a.bits.data := data
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out.a.bits.addr_hi := ~(~address | addressMask) >> log2Ceil(tlDataBytes)
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// TL legacy does not support bus errors
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assert (!out.d.valid || !out.d.bits.error)
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// Recreate the beat address counter
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val beatCounter = RegInit(UInt(0, width = tlBeatAddrBits))
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when (out.d.fire() && edge.hasData(out.d.bits) && out.d.bits.size === block) {
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beatCounter := beatCounter + UInt(1)
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}
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val grant = io.legacy.grant.bits
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grant.g_type := MuxLookup(out.d.bits.opcode, Grant.prefetchAckType, Array(
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TLMessages.AccessAck -> Grant.putAckType,
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TLMessages.AccessAckData -> Mux(out.d.bits.size === beat, Grant.getDataBeatType, Grant.getDataBlockType),
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TLMessages.HintAck -> Grant.prefetchAckType))
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grant.is_builtin_type := Bool(true)
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grant.client_xact_id := out.d.bits.source
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grant.manager_xact_id := out.d.bits.sink
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grant.data := out.d.bits.data
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grant.addr_beat := beatCounter
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// Tie off unused channels
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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