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AddressDecoder.scala
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tilelink2 AddressDecoder: improved heuristic
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2016-09-16 16:09:00 -07:00 |
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Buffer.scala
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tilelink2: add a clock crossing adapter
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2016-09-13 18:33:56 -07:00 |
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Bundles.scala
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Crossing.scala
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Edges.scala
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tilelink2 HintHandler: fill in correct sink in responses
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2016-09-12 17:26:40 -07:00 |
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Example.scala
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Merge remote-tracking branch 'origin/master' into black_box_regs
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2016-09-09 13:12:52 -07:00 |
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Fragmenter.scala
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tilelink2: handle bus width=1
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2016-09-15 22:15:11 -07:00 |
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Fuzzer.scala
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First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
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2016-09-13 20:30:14 -07:00 |
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HintHandler.scala
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HintHandler: don't violate Irrevocable rules
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2016-09-15 21:28:56 -07:00 |
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IntNodes.scala
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tilelink2 IntNodes: record interrupt ranges in parameters
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2016-09-08 18:51:43 -07:00 |
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LazyModule.scala
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tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
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2016-09-08 23:06:59 -07:00 |
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Legacy.scala
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testconfigs: disable atomics until AtomicAbsorber finished
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2016-09-15 21:28:56 -07:00 |
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Monitor.scala
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Fix deprecation warnings
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2016-09-16 14:24:19 -07:00 |
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Nodes.scala
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tilelink2: allow := on nodes outside the tilelink2 package
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2016-09-15 21:28:55 -07:00 |
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package.scala
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tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec
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2016-09-08 21:34:20 -07:00 |
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Parameters.scala
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tilelink2: compute minimal decisive mask
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2016-09-15 21:28:56 -07:00 |
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RAMModel.scala
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tilelink2 RAMModel: fix put, get, putAck, getAck case (#282)
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2016-09-13 15:44:36 -07:00 |
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RegField.scala
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RegField: separate UInt=>bytes and bytes=>regs
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2016-09-16 14:24:28 -07:00 |
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RegisterCrossing.scala
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Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
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2016-09-14 17:50:17 -07:00 |
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RegisterRouter.scala
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tilelink2: handle bus width=1
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2016-09-15 22:15:11 -07:00 |
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RegisterRouterTest.scala
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tilelink2 RegisterRouterTest: stall on both edges
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2016-09-14 18:22:12 -07:00 |
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RegMapper.scala
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RegisterRouter: compress register mapping for sparse devices
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2016-09-15 21:28:56 -07:00 |
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SRAM.scala
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tilelink2: add an executable manager parameter
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2016-09-15 21:28:55 -07:00 |
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TLNodes.scala
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[tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both?
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2016-09-14 14:23:23 -07:00 |
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WidthWidget.scala
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Xbar.scala
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tilelink2: refactor address into addr_hi on ABC and addr_lo on CD
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2016-09-06 23:46:44 -07:00 |
