77 lines
2.5 KiB
Scala
77 lines
2.5 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
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{
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val node = TLManagerNode(beatBytes, TLManagerParameters(
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address = List(address),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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fifoId = Some(0))) // requests are handled in order
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// We require the address range to include an entire beat (for the write mask)
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require ((address.mask & (beatBytes-1)) == beatBytes-1)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
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if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
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val mask = bigBits(address.mask >> log2Ceil(beatBytes))
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val in = io.in(0)
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val addrBits = (mask zip in.a.bits.addr_hi.toBools).filter(_._1).map(_._2)
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val memAddress = Cat(addrBits.reverse)
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val mem = SeqMem(1 << addrBits.size, Vec(beatBytes, Bits(width = 8)))
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val d_full = RegInit(Bool(false))
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val d_read = Reg(Bool())
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val d_size = Reg(UInt())
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val d_source = Reg(UInt())
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val d_addr = Reg(UInt())
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val d_data = Wire(UInt())
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// Flow control
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when (in.d.fire()) { d_full := Bool(false) }
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when (in.a.fire()) { d_full := Bool(true) }
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in.d.valid := d_full
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in.a.ready := in.d.ready || !d_full
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val edge = node.edgesIn(0)
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in.d.bits := edge.AccessAck(d_addr, UInt(0), d_source, d_size)
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// avoid data-bus Mux
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in.d.bits.data := d_data
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in.d.bits.opcode := Mux(d_read, TLMessages.AccessAckData, TLMessages.AccessAck)
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val read = in.a.bits.opcode === TLMessages.Get
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val rdata = Wire(Vec(beatBytes, Bits(width = 8)))
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val wdata = Vec.tabulate(beatBytes) { i => in.a.bits.data(8*(i+1)-1, 8*i) }
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d_data := Cat(rdata.reverse)
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when (in.a.fire()) {
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d_read := read
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d_size := in.a.bits.size
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d_source := in.a.bits.source
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d_addr := edge.addr_lo(in.a.bits)
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}
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// exactly this pattern is required to get a RWM memory
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when (in.a.fire() && !read) {
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mem.write(memAddress, wdata, in.a.bits.mask.toBools)
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}
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rdata := mem.read(memAddress, in.a.fire() && read)
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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