Jacob Chang
fe641c14a1
tilelink2: Add support for different noise generator in fuzzer ( #386 )
2016-10-06 13:20:13 -07:00
Andrew Waterman
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
Wesley W. Terpstra
6ec2e7c5bd
tilelink2: Legacy should preserve the access size ( #378 )
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* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
2016-10-03 17:25:31 -07:00
Wesley W. Terpstra
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
c85e42a303
tilelink2: Nodes should accept full PortParameters
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We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
2016-10-03 16:09:49 -07:00
Wesley W. Terpstra
f2ca2178bf
graphML: CTO's like colour
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
fe0875b084
LazyModule: output final verilog Module name
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
52c1a053ff
tilelink2 RegisterRouter: test fully Decoupled behaviour
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
422e6357a4
tilelink2 RegisterCrossing: Queues go from RV to Irrevocable
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AsyncQueue is still a Queue.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
02f89fb530
RegMapper: clarify interface is DecoupledIO
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
8a268268ad
tilelink2 RegField: clarify restrictions on functions
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RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
bff0ffa428
tilelink2 RegisterRouter: fix output data glitches
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If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
2016-10-02 02:24:02 -07:00
mwachs5
9a381e88d1
Suggest sane names for common objects ( #369 )
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* Suggest sane names for common objects frequently instantiated with factory methods
* Suggest names for common primitives using more Scala-esque Options
2016-09-30 16:19:25 -07:00
Wesley W. Terpstra
0ebab0976a
tilelink2 Isolation: add enable signal ( #368 )
2016-09-30 04:54:40 -07:00
Wesley W. Terpstra
d3547a6193
tilelink2: Isolation gate insertion module
2016-09-30 01:50:33 -07:00
Wesley W. Terpstra
9b0654be52
tilelink2 Crossing: helpful constructor objects
2016-09-30 01:48:47 -07:00
Wesley W. Terpstra
80f7bb49e3
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Wesley W. Terpstra
6d8c965f04
tilelink2 Crossing: cut the crossing between clock domains
2016-09-29 17:35:10 -07:00
Wesley W. Terpstra
20f42a8762
tilelink2: reuse the halves of the AsyncQueue
2016-09-29 17:35:08 -07:00
Wesley W. Terpstra
8e4c1e567c
tilelink2: add types for a TL clockless interface
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
02ce8c2ca4
tilelink2 Nodes: rename RootNode => BaseNode
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
754fcf9831
tilelink2: rename BaseNode to SimpleNode
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
cfdb8ca797
tilelink2 LazyModule: remove obsolete connect method
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
f2e438833c
tilelink2 Nodes: generalize a node into inner and outer halves
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This lets us create nodes which transform from one bus to another.
2016-09-29 17:33:11 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
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A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Henry Cook
32f3f94882
[tilelink2] Fix zero-width wires in RAMModel.
2016-09-28 18:02:04 -07:00
Henry Cook
69e121260e
[tilelink2] Add unit tests for many TL2 components
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These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
2016-09-28 18:02:04 -07:00
Henry Cook
81123f84c9
[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. ( #356 )
2016-09-27 18:06:21 -07:00
mwachs5
f9e0a7ac24
Merge branch 'master' into async_register_crossing
2016-09-27 15:54:34 -07:00
Wesley W. Terpstra
eaea138d0d
tilelink2: don't use chisel3 namespace ( #355 )
2016-09-27 14:44:26 -07:00
Henry Cook
f5502df6ab
Merge branch 'master' into async_register_crossing
2016-09-27 14:08:27 -07:00
Wesley W. Terpstra
357d06ac9c
tilelink2 WidthWidget: Gets must have their mask adjusted ( #353 )
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The mask of a Get should also be converted.
This manifested as a bug when going from 32=>64 bits. A large Get
could end up with mask that was not full.
2016-09-27 14:06:02 -07:00
Megan Wachs
3ce08f40a5
crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations
2016-09-27 13:36:28 -07:00
Wesley W. Terpstra
d9e209365d
Tl2 addr width0 ( #346 )
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* tilelink2 Edges: add accessor methods for address and addr_{hi,lo}
* tilelink2: use addr_lo instead of relying on truncation
Truncation can mess up if the width should be 0, but IS 1.
2016-09-26 17:00:03 -07:00
Wesley W. Terpstra
72c205b54f
tilelink2 AddressSet: add .misaligned(low, size) helper method ( #345 )
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This helps devices with misaligned ranges still connect to TL2.
2016-09-26 16:01:09 -07:00
Wesley W. Terpstra
1773eb4405
tilelink2 LazyModule: output GraphML of the bus
2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
35da9320bc
tilelink2 Nodes: expose connectivity in RootNode
2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
d787bae0d0
tilelink2 Xbar: decouple ready from valid ( #338 )
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This moves the Xbar from using custom code to using the Arbiter.
The arbiter has better ready-valid decoupling.
2016-09-23 16:24:29 -07:00
Wesley W. Terpstra
47843d8ec1
tilelink2: maxLgSize should be accurate ( #332 )
2016-09-22 22:06:22 -07:00
Wesley W. Terpstra
c5706afc11
RegField: remove obsolete split method
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This is now natively supported by the regmap(...) invocation.
2016-09-22 20:52:47 -07:00
Wesley W. Terpstra
fc44151f10
RegField: add name and description fields
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In the future we can generate interesting documentation and headers.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
5e34b313ee
RegMapper: regmap(...) now takes BYTE addresses
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If a device has configurable bus-width, we need a stable way of
enumerating registers. The byte offset stays unchanged.
This change also makes it possible to put an arbitrary number of RegFields
starting at some address which are then chopped up into appropriately bus-
sized registers.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
972ca06729
RegField: remove RegField.bytes; it was dangerous
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The implementation unconditionally drove the register.
This made it incompatible with drivers from the device itself.
Besides, writing only parts of a register at a time is ultra-shady.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
a421469754
tilelink2: change adapters to use TLAdapter(params, defaults)(node)
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This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.
For example, this:
peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
2016-09-22 20:52:46 -07:00
Henry Cook
391be8d740
tilelink2 RegisterRouter: minLatency is never more than 1
2016-09-22 15:51:15 -07:00
Wesley W. Terpstra
a3e88fa13a
tilelink2 Atomics: optimize the sign-extension circuit
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ed038678ef
tilelink2 Fuzzer: work around for firrtl/verilator performance issue
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Big Vec()s cause very slow compilation.
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
1e7480b6fc
tilelink2 Monitor: work around for firrtl/verilator performance issue
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Big Vec()s cause problems for these tools.
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ec2030df31
tilelink2 Legacy: convert TL1 atomic operand size
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e5da3eb8bb
tilelink2 Atomics: support arithmetic atomics
2016-09-22 15:18:54 -07:00