85c39b2f97
syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI
2017-08-24 17:47:04 -07:00
4e773f4738
syncregs: Use synchronizer primivites for LevelSyncCrossing
2017-08-24 17:42:31 -07:00
130b24355f
syncregs: Use synchronizer primitives for IntXing
2017-08-24 17:39:07 -07:00
8b462d1595
syncregs: Use common primitives for AsyncQueue grey code synchronizers
2017-08-24 17:34:07 -07:00
3461cb47cc
syncregs: Make Reset catcher use the synchronizer primitive
2017-08-24 17:26:38 -07:00
c78ee9f0e4
syncreg: Refactor common code
2017-08-24 17:18:04 -07:00
d83a6dc6af
syncregs: Add utilities for Synchronizing Shift Registers
2017-08-24 16:55:17 -07:00
bdaae40035
Merge pull request #973 from freechipsproject/named_buffers
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systemBus: allowing naming the TLBuffers which get inserted
2017-08-24 16:31:14 -07:00
7f683eeb24
async_regs: Make modules have predictable names
2017-08-24 15:33:53 -07:00
0f75ebee92
async_reg: Rename the file to match scalastyle
2017-08-24 15:31:29 -07:00
103b6bc6d3
systemBus: allowing naming the TLBuffers which get inserted
2017-08-24 14:49:12 -07:00
17134125e1
SystemBus: remove misnamed functions ( #972 )
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These functions were actually for cross connecting chips.
2017-08-24 23:35:01 +02:00
6e689f55ed
Merge pull request #965 from freechipsproject/quash_x
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async_reset_reg: Squash X's the same as for synchronous reg
2017-08-21 16:48:25 -07:00
81890e3a42
async_reg: Clean up some funky indentation
2017-08-21 16:06:36 -07:00
4f45379863
async_reset_reg: Squash X's the same as for reset reg
2017-08-21 14:33:19 -07:00
82df766f4a
Merge pull request #963 from freechipsproject/interrupt-order
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Respect ISA requirements on interrupt priority order
2017-08-18 00:10:19 -07:00
8087a205cc
Remove redundant check in interrupt priority encoding
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chooseInterrupts already sorts M interrupts above S interrupts.
2017-08-17 22:23:42 -07:00
cbe7c51b50
Respect ISA requirements on interrupt priority order
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a62e76cb16
2017-08-17 21:27:08 -07:00
b1719cfee0
Fixing requirements for PAddrBits ( #961 )
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Previously, the requirement for PAddrBits only checked to be equal or greater than the bundle bits. Changing it to check for these to match exactly as for cases when the PAddrBits greater than address bits we could run into scenarios which cause possible address wrap around issues.
2017-08-17 11:53:59 -07:00
1db4b3be9a
Merge pull request #957 from freechipsproject/param_jtag_vpi
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jtag_vpi: Use Parameterized Black Box
2017-08-14 18:37:30 -07:00
8783d51c97
jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed
2017-08-14 17:25:47 -07:00
710a782145
HeterogenousBag: empty bags were being combined! ( #956 )
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This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.
2017-08-14 15:48:42 -07:00
e945f6e265
Merge pull request #955 from freechipsproject/fix-acquire-before-release
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Fix acquire before release
2017-08-13 18:29:58 -07:00
57a5965bf4
Merge pull request #954 from freechipsproject/max-core-cycles
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Add a +max-core-cycles PlusArg
2017-08-13 16:45:59 -07:00
88332bd885
max-core-cycles: Add a +max-core-cycles PlusArg
2017-08-13 15:47:14 -07:00
3cbc5262ec
Don't permit new acquires until the release queue is drained
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If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
2017-08-13 13:18:45 -07:00
0190724492
Actually use the C-channel acquire-before-release queue
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oops...
2017-08-13 13:03:35 -07:00
41a2a03f90
Merge pull request #953 from freechipsproject/fix-dcache-ecc
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Don't trigger ECC writebacks when a release is in flight
2017-08-12 16:47:19 -07:00
7387f2a93a
Don't block D-channel when handling a probe
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This is an acquire-before-release regression.
2017-08-12 16:13:24 -07:00
604abd5b07
Only report ECC errors when the RAM was actually read
2017-08-12 15:28:03 -07:00
18fb052fc9
DRY
2017-08-12 15:27:30 -07:00
176110b6d3
Don't trigger ECC writebacks when a release is in flight
2017-08-12 15:23:57 -07:00
f191bb994c
PatternPusher: can now expect a certain output ( #952 )
2017-08-11 18:10:27 -07:00
baf769f924
tilelink: add PatternPusher, a device to inject a fixed traffic pattern ( #950 )
2017-08-11 15:07:10 -07:00
a3358f34a0
Fix priority inversion for two back-to-back divides ( #948 )
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If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit. While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
2017-08-10 17:12:09 -07:00
fa867bc478
plusarg_reader: make synthesis path a no brainer ( #947 )
2017-08-10 16:35:30 -07:00
0a591c5b5b
Roll back use of UIntToOH1 ( #946 )
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These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass. This is not yet conclusive.
2017-08-09 18:39:47 -07:00
0b8b136831
Merge pull request #943 from freechipsproject/fix-ibuf
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Fix IBuf bug
2017-08-09 10:38:35 -07:00
721770244e
Fix IBuf bug
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Don't examine a packet's xcpt signal if it might be invalid. In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
2017-08-09 09:47:51 -07:00
fb2c22ca80
Merge pull request #944 from freechipsproject/fix-vlsi-mem-gen
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memgen: also randomize ren and rand register
2017-08-08 23:18:08 -07:00
31b75987ca
Avoid width warning
2017-08-08 20:57:31 -07:00
8705b0e070
memgen: also randomize ren and rand register
2017-08-08 20:41:53 -07:00
97ad528a32
Merge pull request #941 from freechipsproject/bump-riscv-tools
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Bump riscv-tools to bump riscv-tests for mi-csr test fix.
2017-08-08 18:50:29 -07:00
49ba31ac34
Merge pull request #942 from freechipsproject/bus-blocker-lock
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Bus blocker lock
2017-08-08 18:03:36 -07:00
a9b1410f01
BusBlocker: parameterize page granularity
2017-08-08 17:10:01 -07:00
010ba94474
BusBlocker: rename a variable
2017-08-08 17:00:22 -07:00
6d6fc38787
BusBlocker: lock bit should affect the prior PMP address, not next
2017-08-08 17:00:12 -07:00
dd5934b6dc
Bump riscv-tools to bump riscv-tests for mi-csr test fix and pull in stable binutils.
2017-08-08 16:29:26 -07:00
0a351f677d
Merge pull request #940 from freechipsproject/fix-ecc-way
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Don't merge stores that manifest WAW hazards
2017-08-08 16:05:21 -07:00
8cc41ab46b
Merge pull request #936 from freechipsproject/vlsi-mem-gen
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Improve and use vlsi_mem_gen for verilator flow
2017-08-08 16:04:53 -07:00
