Andrew Waterman
fa6ecdf813
Fix RVC/uncacheable instruction memory performance bug
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9c1d126965
was an incomplete fix, so
sometimes we were requesting pipeline replays when they weren't
necessary.
2017-05-03 17:52:06 -07:00
Henry Cook
7b3d87a2e6
Merge pull request #723 from ucb-bar/fuzz-ranges
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Allow TL fuzzing range to be overridden
2017-05-03 16:30:10 -07:00
Henry Cook
1f1240baf1
fuzzer: allow fuzzing range to be overridden
2017-05-03 15:29:14 -07:00
Henry Cook
cd547fabbd
Merge pull request #695 from ucb-bar/pipeline-mmio
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Pipeline AXI4 MMIO
2017-05-03 11:25:24 -07:00
Megan Wachs
f8c92d2669
Merge branch 'master' into pipeline-mmio
2017-05-03 08:37:12 -07:00
Andrew Waterman
4efcb5a139
Increase frontend decoupling ( #722 )
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Reduce pathological RVC stalls
2017-05-03 07:54:46 -07:00
Henry Cook
05ca88fb47
Merge branch 'master' into pipeline-mmio
2017-05-03 01:59:59 -07:00
Megan Wachs
922a8ef5e0
local_interrupts: Correct off-by-1 if there is no SEIP
2017-05-02 21:55:25 -07:00
Henry Cook
4dd3345db2
Merge branch 'master' into pipeline-mmio
2017-05-02 16:23:26 -07:00
Yunsup Lee
1ecd63611f
Merge pull request #718 from ucb-bar/dtim-putpartial
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Add PutPartial support to DTIM
2017-05-02 15:42:28 -07:00
Andrew Waterman
3a1a37d41b
Support PutPartial in ScratchpadSlavePort
2017-05-02 03:07:02 -07:00
Andrew Waterman
938b089543
Remove legacy devices that use AMOALU
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I'm going to change the AMOALU API, and so I'm removing dependent dead code.
2017-05-02 03:05:41 -07:00
Andrew Waterman
f8151ce786
Remove subword load muxing in ScratchpadSlavePort
2017-05-02 00:14:46 -07:00
Andrew Waterman
044b6ed3f9
Improve logical ops in AMOALU
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As with integer ALU, shave off some muxing.
2017-05-02 00:14:46 -07:00
Andrew Waterman
f49172b5bc
ScratchpadSlavePort doesn't support byte/halfword atomics
2017-05-02 00:14:46 -07:00
Wesley W. Terpstra
fe280187a1
axi4: Fragmenter cuts all input channel readys
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AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
3d06f01a2c
rocket: turn on early ack for ITIM
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
58a4529cc5
axi4: the last missing piece for safe FIFO ordering
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
b0b5601e8d
axi4: ToTL correct error handling
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If there is an illegal AWADDR = 0x2 on a 32-bit bus, remapping it
to an aligned address on the error device may make the mask
inconsistent with the address + size.
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
661015a78d
axi4: switch arbiter to round robin
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
976af7a8c7
tilelink2: better width inference for {left,right}OR
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
40f18e6e43
diplomacy: optimize IdRange overlap detection
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
30f1f1e7c7
rocket: turn on early ack for DTIM
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
6ee69454c3
tilelink2: Fragmenter now supports early Ack
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
e09fa866b7
tilelink2: FIFOFixer should NOT change client request status
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Just because some clients are not FIFO does not matter. Downstream
FIFOFixers will still present a legitimate single domain to those
client who care.
2017-05-01 22:53:41 -07:00
Scott Johnson
b040a462c9
Wes's change to remove user bits from external AXI interface, and add 1 cycle latency to make sure external AXI is compliant
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
a71f708dc7
rocketchip: move the Error device to 0x3000
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
d27e1928dd
axi4: make maxFlight a per-master parameter
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e1a072a644
axi4: massage test cases into shape again
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
9f08c484bd
tilelink2: ToAXI4 provide FIFO order semantics
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
61a6f94196
axi4: get unit tests legal again
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
bf5cb396b9
rocketchip: relax mmio no-interleaving requirement
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
24f577c156
axi4: Deinterleaver ensures R channel ID does not change till last
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
b4188ee625
axi4: ToTL supporting pipelined MMIO
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
ca2cb033cd
rocketchip: fix uses of AXI4 Fragmenter
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e100a943ea
axi4: simplify Fragmenter by using user bits
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
7a1d107c9e
rocketchip: include an ErrorSlave by default
2017-05-01 22:53:37 -07:00
Wesley W. Terpstra
641a4d577a
tilelink2: Error device for returning errors on demand
2017-05-01 22:53:02 -07:00
Wesley W. Terpstra
a580b17ece
axi4: IdIndexer => reduce number of needed ids
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
06efc01d96
axi4: an adapter to remove user bits
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
f1217519f1
axi4: RegisterRouter; concurrent response illegal in AXI
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
5163ccd11f
axi4: RegisterRouter supports user bits
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
de6ea9b442
axi4: support user bits in SRAM
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
396ecacda4
AXI4: add an optional user bundle field
2017-05-01 22:53:01 -07:00
Andrew Waterman
d6e69066a5
Fix ITIM loads ( #716 )
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An incorrectly-set ready signal caused bad data to be read from the RAM.
2017-05-01 17:41:25 -07:00
Andrew Waterman
dd85d7e0a0
I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle
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@solomatnikov found the bug. It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
2017-04-28 16:44:58 -07:00
Megan Wachs
d67738204f
Interrupts: Less Pessimistic Synchronization ( #714 )
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* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.
* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC
* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.
* interrupts: use consistent async/periph/core ordering
* interrupts: Properly condition on 0 External interrupts
* interrupts: CLINT is also synchronous to periph clock
2017-04-28 14:49:24 -07:00
Andrew Waterman
9b688ce7e2
Merge pull request #707 from ucb-bar/itim
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ITIM
2017-04-28 02:55:01 -07:00
Andrew Waterman
7416f2a17e
Unbreak groundtest
2017-04-28 02:10:33 -07:00
Andrew Waterman
8fd5ecdff8
Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR
2017-04-27 19:50:38 -07:00