riscv/rocket-chip
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375 Commits

Author SHA1 Message Date
Wesley W. Terpstra
48c7aed4e1 Monitor: any probe supported by the client is legal 2017-03-20 11:34:19 -07:00
Wesley W. Terpstra
c9459fe4eb tilelink2 Xbar: don't use unnecessary ports 2017-03-19 17:02:24 -07:00
Wesley W. Terpstra
7971947d6c tilelink2 Monitor: don't inspect bits if valid is forbidden 2017-03-19 16:34:23 -07:00
Wesley W. Terpstra
db55a1d755 Fragmenter: fix a bug when underlying device supports larger bursts (#589) 2017-03-17 11:00:49 -07:00
Wesley W. Terpstra
882a7ff8ff TLToAPB: use the now standard aFlow parameter name 2017-03-16 15:34:59 -07:00
Wesley W. Terpstra
ca2c709d29 TLBuffer: move TLBufferParams to diplomacy.BufferParams 2017-03-16 15:19:36 -07:00
Wesley W. Terpstra
778c8a5c97 ToAHB: appease AHB VIP 2017-03-16 15:17:05 -07:00
Wesley W. Terpstra
604a164b97 TLToAHB: rename parameter to aFlow 2017-03-16 15:10:54 -07:00
Wesley W. Terpstra
bb49575368 ahb: rewrote TLToAHB to avoid retracting requests on stall 2017-03-16 14:36:30 -07:00
Wesley W. Terpstra
d98fd942f1 tilelink2: optimize the supportsX check circuits 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
3c5c877409 tilelink2: make TLBuffer API more flexible 2017-03-14 14:06:18 -07:00
Wesley W. Terpstra
6fc3ec3d63 tileink2: add a TestRAM; a zero-delay RAM useful for testing 
TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
 2017-03-14 14:06:17 -07:00
Henry Cook
bb0390630c Merge branch 'master' into priv-1.10 2017-03-13 21:40:12 -07:00
Wesley W. Terpstra
eaf474a081 LFSR: use random intial value of the start register 
We just need to make sure it doesn't initialize randomly stuck at 0.
 2017-03-13 13:17:52 -07:00
Henry Cook
1a3fec61c0 Merge branch 'master' into priv-1.10 2017-03-13 11:59:18 -07:00
Wesley W. Terpstra
d2da33e4b1 Fuzzer: use different LFSR seeds based on simulator seed 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
bb6108abd5 Tests: include more random delays 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
0c7fb87390 TLDelayer: insert noise on invalid cycles 2017-03-11 02:53:43 -08:00
Jacob Chang
1c6dde8c15 Make parameters for TLToAHB and TLToAXI4 accessable (#581) 2017-03-10 22:26:38 -08:00
Henry Cook
dbc8f4b30b last => done 2017-03-10 15:58:38 -08:00
Wesley W. Terpstra
d3c5318714 build: remove the now obsolete config string 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
93ca555c20 IntXing: support configurable sync depth 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
38489ad9b0 tilelink2: bring IntNode parameters up to the current standard 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
cfd367248f rocketchip: add blind ports to DTS 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
9a5e2e038b uncore: add DTS meta-data for devices 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
7f6a250dbf tilelink2: add hooks for Resources 2017-03-02 21:19:19 -08:00
Henry Cook
6958f05a85 Merge remote-tracking branch 'origin/master' into periphery-adjustments 2017-02-27 19:40:55 -08:00
Andrew Waterman
dfa61bc487 Standardize Data.holdUnless and SeqMem.readAndHold 
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
  use of holdUnless
 2017-02-25 03:07:49 -08:00
Wesley W. Terpstra
c01aec9259 tilelink2: support unused IntXing 2017-02-22 18:41:06 -08:00
Wesley W. Terpstra
735e4f8ed6 diplomacy: use HeterogeneousBag instead of Vec 
This makes it possible for the bundles to have different widths.

Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities.  This would mean that if
you had two source[] fields, they end up the same.
 2017-02-22 17:05:22 -08:00
Wesley W. Terpstra
5045696f92 TLRational: test all corners 
In order to ensure that verilator is happy, we launch both clocks from a
clock divider.  Sadly, it does not follow the spec wrt.  derived clocks.

See the verilator manual section on "Generated Clocks".
 2017-02-17 14:44:31 +01:00
Wesley W. Terpstra
924afebbd9 tilelink2: make TLRational have configurable direction 2017-02-17 13:59:54 +01:00
Wesley W. Terpstra
abe344a1a4 tilelink2 Fuzzer: support read-only mode (#555) 2017-02-13 00:18:47 +01:00
Henry Cook
e8c8d2af71 Heterogeneous Tiles (#550) 
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
 2017-02-09 13:59:09 -08:00
Wesley W. Terpstra
7aba066e67 tilelink2: add TLZero; /dev/zero suitable for putting behind locked cache ways 2017-02-03 16:20:27 -08:00
Jacob Chang
83a83c778a Added range function in IdRange 
Added source accessor function in TLEdge
 2017-02-02 12:35:57 -08:00
Wesley W. Terpstra
e5af59db68 rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
Wesley W. Terpstra
f7f52cc722 diplomacy: restore Monitor functionality 2017-01-29 17:25:14 -08:00
Wesley W. Terpstra
972953868c uncore: switch to new diplomacy Node API 
Most adapters should work on multiple ports.
This patch changes them all.
 2017-01-29 15:54:45 -08:00
Wesley W. Terpstra
830d01329d RationalCrossing: add some documentation 2017-01-26 21:27:34 -08:00
Wesley W. Terpstra
fc3b72084f tilelink2: add a rational clock crossing adapter 2017-01-26 20:07:28 -08:00
Wesley W. Terpstra
4b70386393 AsyncCrossing: disambiguate the file name 2017-01-26 20:07:28 -08:00
Wesley W. Terpstra
6ff35a387a tilelink2: disable A=>D bypass in ToAXI4 whenever possible 2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
64e1de751d axi4: add a minLatency parameter 2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
c0b6d31377 tilelink2: Delayer adapter useful for unit tests 2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
9dc7f180b6 diplomacy: support zero-port Nodes 2017-01-19 19:08:01 -08:00
Wesley W. Terpstra
e7b35b4bb6 diplomacy: support multiple ports behind a BlindNode 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
4bdb2e5d68 tilelink2 Monitor: ReleaseAck source does not count 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
fbf1073586 tilelink2: CacheCork - terminate caching 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
bf7823f1c8 tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
Jacob Chang
c531093898 Fix bug introduced with Fuzzer when nOperations is power of 2 (#492) 2016-12-15 19:10:53 -08:00
Wesley W. Terpstra
a9b264e582 ahb: lower hsel when idle to save power 2016-12-15 15:32:30 -08:00
Wesley W. Terpstra
16febe7e94 apb: add a TileLink to APB bridge and unittest it 2016-12-15 15:32:27 -08:00
Wesley W. Terpstra
a5b8fc2317 RegisterRouterTest: start up with 0 in registers to make VIP testing easier 2016-12-14 15:38:08 -08:00
Jacob Chang
aae9b23036 Update with paratermized LazyModule 2016-12-12 16:16:56 -08:00
Jacob Chang
762afcd54a Merge remote-tracking branch 'origin/master' into jchang_test 2016-12-09 16:56:49 -08:00
Jacob Chang
4c3083c181 Remove unnecessary val 2016-12-09 16:44:30 -08:00
Wesley W. Terpstra
51dfb9cb06 ahb: TileLink master 2016-12-08 18:00:39 -08:00
Jacob Chang
54cc071a64 Fix Fragmenter to ensure logical operations must be sent out atomically. 
Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
 2016-12-07 16:22:05 -08:00
Wesley W. Terpstra
c2eedbfe23 tilelink2 Monitor: use Parameters instead of global variables 2016-12-07 12:24:03 -08:00
Wesley W. Terpstra
020fbe8be9 diplomacy: make config.Parameters available in bundle connect() 
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
 2016-12-07 12:24:01 -08:00
Wesley W. Terpstra
fbfa15efea TLBroadcast: support non-FIFO devices (#482) 2016-12-05 22:10:37 -08:00
Jacob Chang
cff2612cdb minor Changes needed to support formal tests 2016-12-01 15:02:23 -08:00
Wesley W. Terpstra
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
30e890b480 diplomacy: include InternalNodes for AXI4 and TL 2016-11-23 20:44:45 -08:00
Henry Cook
38c5af5bad [rocket] cleanup mshr logic 2016-11-23 12:09:56 -08:00
Wesley W. Terpstra
1d3cad3671 tilelink2 SourceShrinker: handle degenerate cases for free 2016-11-22 22:17:30 -08:00
Wesley W. Terpstra
c0b27999ea tilelink2 SourceShrinker: a concurrency reducing adapter 2016-11-22 21:43:38 -08:00
Wesley W. Terpstra
0097274ea3 Broadcast: single-cycle response is possible 2016-11-22 20:45:40 -08:00
Henry Cook
c31b41a7ac [tl2] add grant finisher comment 2016-11-19 19:16:43 -08:00
Henry Cook
8b908465e0 [tl2] convert NBDcache to TL2 (WIP; compiles but untested) 2016-11-18 19:04:06 -08:00
Henry Cook
5f1cc19d71 [tl2] fix comment explaining permissions 2016-11-18 19:02:17 -08:00
Henry Cook
10112da4e7 [tl2] won't need putthrough opcode 2016-11-18 19:02:17 -08:00
Wesley W. Terpstra
03bca77b33 tilelink2 Metadata: cannot assert data good when !valid 2016-11-18 17:16:12 -08:00
Wesley W. Terpstra
37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
Henry Cook
94086f2270 [tl2] broadcast hub probe port width bugfix 2016-11-17 18:42:59 -08:00
Henry Cook
960c2723ab [tl2] MemoryOpCategories: use def to supply Cat'd consts 2016-11-17 18:42:59 -08:00
Wesley W. Terpstra
dfc3a0dafb tilelink2: do not depend on obsolete TL1 configuration 2016-11-17 14:07:53 -08:00
Henry Cook
24e3216fcf coreplex: allow zero interrupt sink/sources 2016-11-16 16:50:36 -08:00
Henry Cook
479bc82f03 tilelink2 Broadcast: improve bufferless throughput 2016-11-16 16:50:36 -08:00
Henry Cook
1f51564577 [rocket] dcache probe ack data bugfix 2016-11-16 14:25:21 -08:00
Wesley W. Terpstra
5d2e637a4a tilelink2 Legacy: uncached TL never needs manager_xact_id 2016-11-16 12:16:25 -08:00
Wesley W. Terpstra
10e459fedb rocket: change connection between rocketchip and coreplex 
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
 2016-11-15 18:27:52 -08:00
Wesley W. Terpstra
ab3dafb8bc Monitor: restore Probe&Acquire checks 2016-11-14 15:36:52 -08:00
Henry Cook
c0efd247b0 [tl2] expand firstlast api and L1WB bugfix 2016-11-14 12:12:31 -08:00
Henry Cook
b7730d66f2 WIP bugfixes: run until corrupted WB data (beats repeated) 2016-11-11 18:34:48 -08:00
Henry Cook
afa1a6d549 WIP uncore and rocket changes compile 2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
9d77e34bee tilelink2 Filter: make transfer cap robust against large filters 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
b8df59f43b tilelink2 Broadcast: support "bufferless" implementation 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
14800f8fb4 tilelink2 Broadcast: only support caching readable devices 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
0f3947bb86 tilelink2 Broadcast: add special case handling for 0 cached clients 2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
ba3c83287f tilelink2 Xbar: merge the AddressSets of fractured managers 2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
55326c29bb tilelink2: Filter adapter removes some of the address space 2016-11-03 22:18:23 -07:00
Wesley W. Terpstra
86ba94781b tilelink2: broadcast coherence manager 2016-11-03 14:37:19 -07:00
Wesley W. Terpstra
d067e87a7d tilelink2 Parameters: sinkId is per port, not per manager 2016-11-03 14:37:17 -07:00
Wesley W. Terpstra
ed4224dde4 tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull 
If we send out the PutFull portion of an AMO, the slave is allowed
to respond with AccessAck on the same cycle. In this case, we are
still in the AMO state, but must still match the D response.
 2016-10-31 15:17:10 -07:00
Wesley W. Terpstra
ba529c3716 rocketchip: use TileLink2 interrupts 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
043ed48c8c tilelink2 HintHandler: delay answers to help TL1 legacy clients 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
015c3b862a diplomacy: print out bus widths on edges in agent graph 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
545154c1c3 groundtest: make it happy with TL2 addressing 2016-10-31 11:42:47 -07:00