solomatnikov
274d908d98
Changed TLXbar arbitration policy to roundRobin ( #781 )
2017-06-05 10:20:28 -07:00
Andrew Waterman
efce8f06b8
Merge pull request #769 from freechipsproject/new-div-sqrt
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Incorporate new div/sqrt unit
2017-06-03 03:58:52 -07:00
Andrew Waterman
16ecbdd5b2
Reduce fanout on critical I$ miss signal
2017-06-02 20:45:50 -07:00
Andrew Waterman
27b143013f
Improve ITLB QoR
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- No need to check cacheability
- Remove a gate delay from PMP path
2017-06-02 20:45:50 -07:00
Andrew Waterman
0ffb2c8baf
Simplify and improve QoR of ShiftQueue
2017-06-02 20:44:52 -07:00
Andrew Waterman
8229bdee03
Remove FP unboxing from FMA critical path
2017-06-02 20:44:52 -07:00
Andrew Waterman
7504b47bbe
Improve code quality in FP->FP and Int->FP units
2017-06-02 20:44:52 -07:00
Andrew Waterman
84c4ae775f
Improve QoR for FP->Int conversions
2017-06-02 20:44:52 -07:00
Andrew Waterman
07968df183
Refactor FP Classify
2017-06-02 20:44:52 -07:00
Andrew Waterman
6ecd58a977
Incorporate new div/sqrt unit
2017-06-02 20:44:15 -07:00
Wesley W. Terpstra
b1917e7915
coreplex: add an ISPPort trait to add cross-connect points
2017-06-02 20:43:23 -07:00
Wesley W. Terpstra
81d372137a
coreplex: unconditionally insert a Splitter between tiles and l1tol2
2017-06-02 20:43:21 -07:00
Wesley W. Terpstra
d002cec6ac
NodeNumberer: add an adapter to map inter-chip fabrics
2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
5a2a6b0386
diplomacy: add a CustomNode type that allows direct overload of methods
2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
fed1f53afa
tilelink2: add a TLSplitter to be used for the ISP port
2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
a4bf678954
tilelink2: fix latent Xbar truncation bug
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This was introduced when we switched to HeterogeneousBag for diplomatic IO.
It seems a lucky coincidence that nothing has run into this yet!
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
ce12a64f4b
tilelink2: support SplitterNodes
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
de39af7f65
tilelink2: make some Xbar methods reusable
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
0a2a93c27d
diplomacy: add the new Splitter node type
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
c695237050
diplomacy: make :=* and :*= resolution more flexible
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
4679545b60
travis: front-load the longer running tests and tolerate no output ( #779 )
2017-06-02 20:41:26 -07:00
edwardcwang
cdbf67be68
Add a note to wire up jtag_mfr_id ( #778 )
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Close #774
2017-06-02 18:53:14 -07:00
Wesley W. Terpstra
63b1f4f047
Merge pull request #777 from freechipsproject/print-axi-ids
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coreplex: Improve memory map and AXI ID map output
2017-06-02 18:52:55 -07:00
Wesley W. Terpstra
e0741a2097
axi4: don't map unused masters into TL source ID space
2017-06-02 16:30:16 -07:00
Wesley W. Terpstra
6b7a9f0c95
Revert "Bump firrtl to get performance bug fixes ( #772 )"
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This reverts commit 8e45dd9352
2017-06-02 15:52:32 -07:00
Wesley W. Terpstra
80c63c0da6
rocket: include hartid in cache master names
2017-06-02 15:52:23 -07:00
Wesley W. Terpstra
d25ad10592
diplomacy: require masters to have a name
2017-06-02 15:52:20 -07:00
Wesley W. Terpstra
475ac93cdf
coreplex: print memory map using DTS, also write a JSON for it
2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
ae8734da05
diplomacy: report cacheability in ResourceAddress
2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
985d9750e6
tilelink2: Xbar QoR improvement
2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
9317a00896
tilelink2: ToAXI4, sort and print AXI IDs used
2017-06-02 14:27:37 -07:00
Wesley W. Terpstra
38e6512c0f
Merge pull request #775 from freechipsproject/unify-only-at-end
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Unify only at end
2017-06-01 17:16:48 -07:00
Wesley W. Terpstra
eb14329c63
tilelink2: only combine managers of the same resources
2017-06-01 15:34:43 -07:00
Wesley W. Terpstra
1f531b1593
tilelink2: improve round robin arbiter QoR
2017-06-01 15:34:40 -07:00
Wesley W. Terpstra
5994714970
diplomacy: move manager unification to meta-data only
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Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
2017-06-01 15:30:20 -07:00
Wesley W. Terpstra
0fe625c52f
diplomacy: improve PMA circuit QoR
2017-06-01 15:30:20 -07:00
Wesley W. Terpstra
dfb6340927
Merge pull request #755 from freechipsproject/verilator-plusargs
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Verilator plusargs
2017-06-01 14:34:09 -07:00
Wesley W. Terpstra
6a7e6ab325
plusarg_reader: support verilator
2017-06-01 10:59:45 -07:00
Wesley W. Terpstra
9eae1fa377
verilator: bump to version 3.904
2017-06-01 10:59:39 -07:00
Yunsup Lee
6124bf0cc2
sort entires in the printed address map ( #773 )
2017-05-31 07:45:46 -10:00
Jack Koenig
8e45dd9352
Bump firrtl to get performance bug fixes ( #772 )
2017-05-30 20:21:29 -07:00
Megan Wachs
8d04e0efb8
Merge pull request #771 from freechipsproject/jtag_vpi_tab
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JTAG VPI: Make it work without debug_pp flag
2017-05-30 17:29:23 -07:00
Megan Wachs
6aa13b4e01
JTAG VPI: Make it work without debug_pp flag
2017-05-30 15:46:45 -07:00
Megan Wachs
f61e30763f
Merge pull request #768 from freechipsproject/flush_jtag_vpi
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jtag_vpi: Attempt to more aggressively flush the simulator output
2017-05-26 15:51:43 -07:00
Jacob Chang
e3e77d68e6
PTW now does not require atomic memory operations, so take out the requirement ( #767 )
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Bug fix in CSR which manifest itself when compiling a config with no extension
2017-05-26 13:11:15 -07:00
Megan Wachs
0493372027
jtag_vpi: Attempt to more aggressively flush the simulator output as it is needed by other listeners
2017-05-26 11:48:45 -07:00
Andrew Waterman
618468a06b
Make plusarg_reader default args work with VCS ( #765 )
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Resolves #764
2017-05-24 21:38:56 -07:00
Andrew Waterman
dbc5e7c494
Add TLB miss performance counters ( #762 )
2017-05-23 12:52:25 -07:00
Andrew Waterman
b2b4c1abcd
Separate tag ECC and data ECC options ( #761 )
2017-05-23 12:51:48 -07:00
Henry Cook
940614625e
TLCacheCork: unsafe flag now _really_ unsafe ( #760 )
2017-05-22 19:37:11 -07:00
