Jacob Chang
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aae9b23036
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Update with paratermized LazyModule
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2016-12-12 16:16:56 -08:00 |
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Jacob Chang
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762afcd54a
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Merge remote-tracking branch 'origin/master' into jchang_test
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2016-12-09 16:56:49 -08:00 |
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Jacob Chang
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4c3083c181
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Remove unnecessary val
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2016-12-09 16:44:30 -08:00 |
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Wesley W. Terpstra
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09afbbafdb
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ahb: weaken RegisterRouter assertion
As written I think it could potentially fail, but what I actually care
about is something weaker that should be true. Assert: nothing lost.
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2016-12-08 18:00:39 -08:00 |
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Wesley W. Terpstra
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588b944ed4
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ahb: implement and test address decoding
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2016-12-08 18:00:39 -08:00 |
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Wesley W. Terpstra
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5d1064fcb1
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ahb: include a unit test
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2016-12-08 18:00:39 -08:00 |
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Wesley W. Terpstra
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51dfb9cb06
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ahb: TileLink master
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2016-12-08 18:00:39 -08:00 |
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Wesley W. Terpstra
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01b0f6a52b
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ahb: new diplomacy-based AHB bus definition
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2016-12-08 18:00:39 -08:00 |
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Jacob Chang
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54cc071a64
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Fix Fragmenter to ensure logical operations must be sent out atomically.
Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
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2016-12-07 16:22:05 -08:00 |
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Wesley W. Terpstra
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c2eedbfe23
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tilelink2 Monitor: use Parameters instead of global variables
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2016-12-07 12:24:03 -08:00 |
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Wesley W. Terpstra
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020fbe8be9
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diplomacy: make config.Parameters available in bundle connect()
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
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2016-12-07 12:24:01 -08:00 |
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Wesley W. Terpstra
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fbfa15efea
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TLBroadcast: support non-FIFO devices (#482)
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2016-12-05 22:10:37 -08:00 |
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Wesley W. Terpstra
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3c9718ec8f
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clint: undefined registers must be zero (#480)
This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
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2016-12-05 17:11:53 -08:00 |
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Jacob Chang
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cff2612cdb
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minor Changes needed to support formal tests
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2016-12-01 15:02:23 -08:00 |
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Wesley W. Terpstra
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b7963eca4e
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copyright: ran scripts/modify-copyright
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2016-11-27 22:15:43 -08:00 |
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Wesley W. Terpstra
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a0e10aec05
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uncore: removed obsolete Builder file
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2016-11-27 22:15:43 -08:00 |
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Wesley W. Terpstra
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30e890b480
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diplomacy: include InternalNodes for AXI4 and TL
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2016-11-23 20:44:45 -08:00 |
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Henry Cook
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38c5af5bad
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[rocket] cleanup mshr logic
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2016-11-23 12:09:56 -08:00 |
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Henry Cook
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dae6772624
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factor out common cache subcomponents into uncore.util
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2016-11-23 12:09:35 -08:00 |
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Wesley W. Terpstra
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1d3cad3671
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tilelink2 SourceShrinker: handle degenerate cases for free
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2016-11-22 22:17:30 -08:00 |
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Wesley W. Terpstra
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c0b27999ea
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tilelink2 SourceShrinker: a concurrency reducing adapter
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2016-11-22 21:43:38 -08:00 |
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Wesley W. Terpstra
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0097274ea3
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Broadcast: single-cycle response is possible
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2016-11-22 20:45:40 -08:00 |
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Wesley W. Terpstra
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c80ee06472
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rocketchip: configString is a lazy property of outer
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2016-11-22 17:27:58 -08:00 |
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Henry Cook
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28c6be90ab
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[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
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2016-11-20 19:36:51 -08:00 |
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Henry Cook
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c31b41a7ac
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[tl2] add grant finisher comment
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2016-11-19 19:16:43 -08:00 |
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Wesley W. Terpstra
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d1328a6b6f
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rocketchip: remove most uses of GlobalAddrMap
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2016-11-18 19:38:02 -08:00 |
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Henry Cook
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8b908465e0
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[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
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2016-11-18 19:04:06 -08:00 |
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Henry Cook
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5f1cc19d71
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[tl2] fix comment explaining permissions
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2016-11-18 19:02:17 -08:00 |
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Henry Cook
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10112da4e7
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[tl2] won't need putthrough opcode
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2016-11-18 19:02:17 -08:00 |
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Wesley W. Terpstra
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5b594ced29
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Plic: support 0 interrupts gracefully
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2016-11-18 18:07:44 -08:00 |
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Wesley W. Terpstra
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03bca77b33
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tilelink2 Metadata: cannot assert data good when !valid
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2016-11-18 17:16:12 -08:00 |
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Wesley W. Terpstra
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37a3c22639
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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Wesley W. Terpstra
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e5febcfa33
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rocketchip: there are no more useful parameters to dump
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2016-11-18 14:31:42 -08:00 |
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Wesley W. Terpstra
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30425d1665
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rocketchip: eliminate all Knobs
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2016-11-18 14:31:42 -08:00 |
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Wesley W. Terpstra
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119ccae9af
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rocketchip: don't use explicit cde namespace
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2016-11-18 14:31:42 -08:00 |
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Henry Cook
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94086f2270
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[tl2] broadcast hub probe port width bugfix
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2016-11-17 18:42:59 -08:00 |
|
Henry Cook
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960c2723ab
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[tl2] MemoryOpCategories: use def to supply Cat'd consts
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2016-11-17 18:42:59 -08:00 |
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Wesley W. Terpstra
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dfc3a0dafb
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tilelink2: do not depend on obsolete TL1 configuration
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2016-11-17 14:07:53 -08:00 |
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Henry Cook
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24e3216fcf
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coreplex: allow zero interrupt sink/sources
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2016-11-16 16:50:36 -08:00 |
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Henry Cook
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479bc82f03
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tilelink2 Broadcast: improve bufferless throughput
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2016-11-16 16:50:36 -08:00 |
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Henry Cook
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1f51564577
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[rocket] dcache probe ack data bugfix
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2016-11-16 14:25:21 -08:00 |
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Wesley W. Terpstra
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5d2e637a4a
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tilelink2 Legacy: uncached TL never needs manager_xact_id
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2016-11-16 12:16:25 -08:00 |
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Wesley W. Terpstra
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10e459fedb
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rocket: change connection between rocketchip and coreplex
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
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2016-11-15 18:27:52 -08:00 |
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Wesley W. Terpstra
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ab3dafb8bc
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Monitor: restore Probe&Acquire checks
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2016-11-14 15:36:52 -08:00 |
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Wesley W. Terpstra
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385b5d5698
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axi4: default should be GET_EFFECTS
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2016-11-14 15:19:39 -08:00 |
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Henry Cook
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c0efd247b0
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[tl2] expand firstlast api and L1WB bugfix
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2016-11-14 12:12:31 -08:00 |
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Henry Cook
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b7730d66f2
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WIP bugfixes: run until corrupted WB data (beats repeated)
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2016-11-11 18:34:48 -08:00 |
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Henry Cook
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71315d5cf5
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WIP scala compile and firrtl elaborate; monitor error
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2016-11-11 13:07:45 -08:00 |
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Henry Cook
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afa1a6d549
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WIP uncore and rocket changes compile
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2016-11-10 15:57:29 -08:00 |
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Wesley W. Terpstra
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9d77e34bee
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tilelink2 Filter: make transfer cap robust against large filters
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2016-11-04 13:35:36 -07:00 |
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