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Commit Graph

680 Commits

Author SHA1 Message Date
Henry Cook
619929eba1 Added coherence tile function defs, with traits and constants 2012-02-16 00:16:45 -08:00
Andrew Waterman
1b5e39e7fc fix bug in BTB
a BTB update followed by a taken branch could cause incorrect control flow.
2012-02-15 21:36:08 -08:00
Andrew Waterman
fc5ba769da disable vector unit by default 2012-02-15 18:58:41 -08:00
Andrew Waterman
8b3b3abd3d fix external memory request nack logic 2012-02-15 18:57:40 -08:00
Andrew Waterman
fe2c1d1321 add vec->ctrl fences 2012-02-15 18:31:19 -08:00
Yunsup Lee
82cd3625c2 add in vackq interface 2012-02-15 17:53:24 -08:00
Andrew Waterman
c13524ad3a fix vcmdq full replay logic 2012-02-15 17:49:12 -08:00
Yunsup Lee
258d050e1b add stall logic for vector command queues 2012-02-15 14:48:41 -08:00
Yunsup Lee
32bdf5098a refactor vector control logic & datapath in the rocket core 2012-02-15 13:30:22 -08:00
Yunsup Lee
7c11c1406c vector-vector add working! 2012-02-15 02:28:07 -08:00
Yunsup Lee
6bdf9dc513 hwacha integration: now it compiles correctly! 2012-02-14 23:34:57 -08:00
Yunsup Lee
a51c7cc927 new build system with updated chisel, hwacha 2012-02-14 19:43:59 -08:00
Andrew Waterman
0ec7767c13 declaring success on FPU for now 2012-02-14 19:11:57 -08:00
Andrew Waterman
297223a13c squash subsequent external mem request after nack 2012-02-14 15:12:16 -08:00
Andrew Waterman
38c67e5a9e add fmin.[s|d] and fmax.[s|d] 2012-02-14 06:37:18 -08:00
Andrew Waterman
ee9fc10668 add fcvt.s.d, fcvt.d.s 2012-02-14 06:03:43 -08:00
Andrew Waterman
ce202c73d1 add fsgnj[n|x].[s|d] 2012-02-14 04:24:35 -08:00
Andrew Waterman
1d604bcd49 remove top-level Makefile
new, simpler build instructions are in the README.
note that for "make run-asm-tests-debug" you need to update your fesvr.
2012-02-14 02:53:43 -08:00
Andrew Waterman
15dc2d8c40 add fp writeback arbitration logic 2012-02-14 00:32:25 -08:00
Henry Cook
0671a99712 NBcache works with associativities other than powers of 2 2012-02-13 21:44:32 -08:00
Henry Cook
6d36168183 Fixed two associative nbcache bugs, one in amo replays and one in the flush unit 2012-02-13 21:44:32 -08:00
Andrew Waterman
0366465cb1 parameterize the scoreboards 2012-02-13 18:12:23 -08:00
Andrew Waterman
6c2d8a37ae remove a partial update that makes chisel barf
chisel regards it as a combinational loop, even though it isn't.
2012-02-13 16:45:29 -08:00
Andrew Waterman
c78c738f60 minor cleanups 2012-02-13 03:13:49 -08:00
Andrew Waterman
b5a19a54a3 add fcvt.[s|d].[w|l][u] 2012-02-13 02:01:26 -08:00
Andrew Waterman
a4a9d2312c add fcvt.[w|l][u].[s|d], f[eq|lt|le].[s|d] 2012-02-13 01:30:01 -08:00
Andrew Waterman
069037ff3a add FP recoding 2012-02-12 23:31:50 -08:00
Andrew Waterman
25ecfb9bbc clean up caches
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
2012-02-12 20:32:06 -08:00
Andrew Waterman
08b6517a23 add FP ops mftx, mxtf, mtfsr, mffsr 2012-02-12 20:12:53 -08:00
Andrew Waterman
9bb1558a34 WIP on FPU 2012-02-12 04:36:01 -08:00
Andrew Waterman
50a283d311 move store data generation into EX stage
doing so removes it from the critical path of FP store unrecoding.
2012-02-12 01:35:55 -08:00
Andrew Waterman
725190d0ee update to new chisel 2012-02-11 17:20:33 -08:00
Andrew Waterman
f8b937d590 fix 32-bit divider bug
thanks, torture!

also, tidied up the code a bit.
2012-02-09 03:47:59 -08:00
Andrew Waterman
03ee49f424 fix 32-bit AMOs to upper halves of 64-bit words
thanks, torture!
2012-02-09 03:31:47 -08:00
Yunsup Lee
f47d888feb vvcfgivl and vsetvl works 2012-02-09 02:35:21 -08:00
Andrew Waterman
92493ad153 fix mul/div kill bug
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
2012-02-09 02:26:03 -08:00
Andrew Waterman
128ec567ed make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux.  the benfit
was close to nil, anyway.
2012-02-09 01:34:00 -08:00
Yunsup Lee
fcc8081c4d hook up the vector command queue 2012-02-09 01:28:16 -08:00
Andrew Waterman
8b6b0f5367 add external memory request interface for vec unit 2012-02-08 22:30:45 -08:00
Yunsup Lee
9285a52f25 initial vu integration 2012-02-08 21:43:45 -08:00
Andrew Waterman
10b5a0006c fix mul/div to rd=0 2012-02-08 20:11:57 -08:00
Andrew Waterman
a1855b12c2 clean up queues 2012-02-08 17:55:05 -08:00
Andrew Waterman
990e3a1b34 fix fpu port direction bug 2012-02-08 15:19:26 -08:00
Andrew Waterman
b3f6f9a5fd fix BTB misprediction check for negative addresses
also index BTB with PC, not PC+4
2012-02-08 15:05:28 -08:00
Andrew Waterman
e9da2cf66a improve id/ex datapath
move operand selection into decode stage; simplify bypassing
2012-02-08 06:47:26 -08:00
Andrew Waterman
d471a8b2da arbitrate for LLFU writebacks in MEM stage 2012-02-08 04:21:05 -08:00
Andrew Waterman
ebed56500e fix mul/wb hazard checks
I erroneously assumed that those instructions set id_wen.
2012-02-08 01:56:11 -08:00
Andrew Waterman
5403d069e9 add fp loads/stores 2012-02-07 23:54:25 -08:00
Christopher Celio
1be9d15944 Fixed bug regarding case sensitivity regarding ioICache,ioDCache 2012-02-07 14:07:42 -08:00
Andrew Waterman
fde8e3b696 clean up bypassing/hazard checking a bit 2012-02-06 17:26:45 -08:00