Henry Cook
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2cb4dbae39
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Refactored uncore constants and tilelink data
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2014-04-10 13:19:50 -07:00 |
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Henry Cook
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5a5f69bfca
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finished uncore constant/tilelink data refactor
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2014-04-10 13:13:46 -07:00 |
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Stephen Twigg
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cac04afc25
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Push riscv-tests, riscv-tools. Repository now consistent such that all tests build, pass in spike, in emulator, and in RTL.
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2014-04-08 22:14:16 -07:00 |
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Stephen Twigg
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f643d38672
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Push rocket, riscv-tests, riscv-tools to consistent state (toolchain rebuild required)
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2014-04-08 16:50:52 -07:00 |
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Andrew Waterman
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fb8c7d3da5
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Push rocket
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2014-04-07 23:49:06 -07:00 |
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Andrew Waterman
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817517c663
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Better branch prediction
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2014-04-07 16:08:06 -07:00 |
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Henry Cook
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56f515c255
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first steps in uncore constant/tilelink data refactor
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2014-03-30 09:21:08 -07:00 |
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Donggyu Kim
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16274a84b6
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update fpga testbench
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2014-03-21 16:21:15 -07:00 |
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Yunsup Lee
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8d68ea9e0b
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Merge branch 'master' of github.com:ucb-bar/reference-chip
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2014-03-20 01:46:30 -07:00 |
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Yunsup Lee
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7bbcf920be
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sync up master
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2014-03-20 01:45:23 -07:00 |
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Andrew Waterman
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51808d9982
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Fix minor FP bugs
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2014-03-18 18:37:53 -07:00 |
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Yunsup Lee
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d2c32b048a
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fix bug in htif_fini, need to use vc_handle!
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2014-03-18 01:35:08 -07:00 |
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Andrew Waterman
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0d124d283a
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Write our own vcs main() routine
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2014-03-17 17:02:28 -07:00 |
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Andrew Waterman
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7f23257873
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Print out random seed if test fails
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2014-03-17 15:35:32 -07:00 |
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Andrew Waterman
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fcbbb275aa
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Fix nondeterminism
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2014-03-15 17:35:30 -07:00 |
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Yunsup Lee
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e4b56b5d0e
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generate verilog for rekall
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2014-03-15 15:31:04 -07:00 |
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Andrew Waterman
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b6bf7cfe0c
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push chisel
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2014-03-11 23:56:57 -07:00 |
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Andrew Waterman
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7ac003a4f7
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push hardfloat
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2014-03-11 20:36:39 -07:00 |
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Andrew Waterman
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f04bde75fb
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New FP encoding
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2014-03-11 19:12:20 -07:00 |
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Yunsup Lee
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6951333a08
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push rocket
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2014-03-04 23:43:00 -08:00 |
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Andrew Waterman
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d055c0ebaf
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Push rocket/hardfloat/chisel
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2014-03-04 16:39:06 -08:00 |
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Yunsup Lee
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23045ec379
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add hwacha vfmsv instructions, keepcfg bug fix, turn off secondary fconv
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2014-03-02 03:38:06 -08:00 |
|
Yunsup Lee
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49f0e43ed1
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push riscv-tools
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2014-03-01 03:31:03 -08:00 |
|
Yunsup Lee
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e20d50436a
|
committed in the wrong directory, meant to commit in the hwacha directory
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2014-03-01 00:01:35 -08:00 |
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Yunsup Lee
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8c459df3b6
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flush deck when xcpt occurs, fixes remaining p test bugs
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2014-02-28 22:50:34 -08:00 |
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Adam Izraelevitz
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cb14baab88
|
Reformatted hammer directory, added parent scripts to repo, as well as README.
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2014-02-28 15:57:46 -08:00 |
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Yunsup Lee
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0c4442c172
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push tests/tools
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2014-02-27 20:28:19 -08:00 |
|
Yunsup Lee
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bcfcdefe88
|
update hwacha
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2014-02-27 04:39:12 -08:00 |
|
Yunsup Lee
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46714c0c60
|
more improvements to hwacha
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2014-02-26 21:20:53 -08:00 |
|
Yunsup Lee
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a5625de3d5
|
support vector irq tests
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2014-02-25 21:18:03 -08:00 |
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Ben Keller
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fcfc1078f8
|
Merge branch 'master' of github.com:ucb-bar/reference-chip
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2014-02-25 15:54:19 -08:00 |
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Yunsup Lee
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220076506c
|
push hwacha; all vector p/v/pt tests work now
|
2014-02-25 03:51:15 -08:00 |
|
Yunsup Lee
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e5c2bd5e7b
|
add extensions option to riscv-dis for better disassembly
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2014-02-25 03:50:32 -08:00 |
|
Yunsup Lee
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8acc9510c4
|
push hwacha,chisel
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2014-02-24 01:43:55 -08:00 |
|
Yunsup Lee
|
22345dd073
|
push rocket,hwacha
|
2014-02-22 22:53:24 -08:00 |
|
Adam Izraelevitz
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f14f386b4f
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Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse
Conflicts:
src/main/scala/ReferenceChip.scala
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2014-02-19 15:50:28 -08:00 |
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Adam Izraelevitz
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a006bffca4
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Merge branch 'master' of github.com:ucb-bar/reference-chip into dse
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2014-02-19 15:04:03 -08:00 |
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Adam Izraelevitz
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58d2e62e3f
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Merge branch 'master' of github.com:ucb-bar/reference-chip into dse
Conflicts:
chisel
src/main/scala/ReferenceChip.scala
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2014-02-19 14:24:36 -08:00 |
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Andrew Waterman
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de965d558a
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Renumber uarch CSRs into custom CSR space
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2014-02-14 17:41:17 -08:00 |
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Andrew Waterman
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e554f6728d
|
Update chisel
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2014-02-14 17:41:17 -08:00 |
|
Stephen Twigg
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755293d785
|
Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha).
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2014-02-14 10:12:09 -08:00 |
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Stephen Twigg
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6808245bb5
|
Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging.
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2014-02-12 16:50:13 -08:00 |
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Andrew Waterman
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e5de170215
|
Update Chisel, fixing Verilog backend
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2014-02-12 14:28:43 -08:00 |
|
Adam Izraelevitz
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e25c54e998
|
Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse
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2014-02-12 13:52:24 -08:00 |
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Adam Izraelevitz
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c1e544886f
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Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse
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2014-02-12 13:35:12 -08:00 |
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Adam Izraelevitz
|
1a03a64572
|
Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse
|
2014-02-12 12:44:30 -08:00 |
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Adam Izraelevitz
|
aae5f465c1
|
Merge branch 'master' of github.com:ucb-bar/reference-chip into dse
Conflicts:
src/main/scala/ReferenceChip.scala
|
2014-02-11 17:31:55 -08:00 |
|
Adam Izraelevitz
|
548cf16061
|
Added jack Makefile and hammer.scala, as well as changed reference chip to have multiple datacache sizes. Requires chisel branch dse
|
2014-02-11 14:36:47 -08:00 |
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Andrew Waterman
|
0ebb115a3c
|
Revert to old AUIPC definition
|
2014-02-10 19:05:14 -08:00 |
|
Scott Beamer
|
cda46b3ce1
|
use --recursive to populate all submodules. with current instructions you can't run tests because riscv-tests/env isn't pulled in
|
2014-02-06 16:20:48 -08:00 |
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