Wesley W. Terpstra
fbf1073586
tilelink2: CacheCork - terminate caching
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
bf7823f1c8
tilelink2: split suportsAcquire into T and B variants
2017-01-19 19:07:13 -08:00
Henry Cook
c1b7c84f09
[rocket] bugfix: RoccExampleConfig looks up PAddrBits too early
2017-01-19 17:48:04 -08:00
Henry Cook
e0411c6cde
[coreplex] bugfix: re-enable multicore configs via WithNCores
2017-01-19 17:48:04 -08:00
Henry Cook
307f938b88
[rocket] bugfix: fixes #517
2017-01-19 17:48:04 -08:00
Megan Wachs
e22b01a6fa
jtag_dtm: Update regression to run and pass.
2017-01-18 12:08:13 -08:00
Henry Cook
9a6634cd40
Add TLBuffers on the L1 backends and blind exit points ( #513 )
...
* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
2017-01-17 11:57:23 -08:00
Henry Cook
74b6a8d02b
Refactor Tile to use cake pattern ( #502 )
...
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
2017-01-16 18:24:08 -08:00
Wesley W. Terpstra
52bb6cd9d9
Configs: use a uniform syntax without Match exceptions ( #507 )
...
* Configs: use a uniform syntax without Match exceptions
The old style of specifying Configs used total functions. The only way to
indicate that a key was not matched was to throw an exception. Not only was
this a performance concern, but it also caused confusing error messages
whenever you had a match failure from a lookup within a lookup. The
exception could get handled by an outer-lookup that then reported the wrong
key as missing.
2017-01-13 14:41:19 -08:00
Jacob Chang
59eb7c24ee
Add iterator function to LazyModule to iterate over all nodes
2017-01-12 15:21:10 -08:00
Andrew Waterman
71c4b000b3
Don't special-case power-of-2 replacement policy for BTB
...
PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage. Regardless,
this should be a second-order effect, so using FIFO always is fine.
2017-01-11 13:21:55 -08:00
Jacob Chang
c531093898
Fix bug introduced with Fuzzer when nOperations is power of 2 ( #492 )
2016-12-15 19:10:53 -08:00
Wesley W. Terpstra
a9b264e582
ahb: lower hsel when idle to save power
2016-12-15 15:32:30 -08:00
Wesley W. Terpstra
16febe7e94
apb: add a TileLink to APB bridge and unittest it
2016-12-15 15:32:27 -08:00
Wesley W. Terpstra
ed091f55e6
apb: diplomatic APB framework
2016-12-15 13:48:50 -08:00
Wesley W. Terpstra
a5b8fc2317
RegisterRouterTest: start up with 0 in registers to make VIP testing easier
2016-12-14 15:38:08 -08:00
Wesley W. Terpstra
9d50704b64
ahb: don't violate spec with SRAM fuzzing
2016-12-14 15:18:41 -08:00
Jacob Chang
2dd9e522a0
Merge branch 'master' into jchang_test
2016-12-12 20:02:53 -08:00
Henry Cook
540502f96d
Convert frontend and icache to diplomacy/tl2 ( #486 )
...
* [rocket] file capitalization
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
2016-12-12 17:38:55 -08:00
Jacob Chang
531f3684ed
Removing module list for merging. (will need to create iterator in future)
2016-12-12 16:25:31 -08:00
Jacob Chang
aae9b23036
Update with paratermized LazyModule
2016-12-12 16:16:56 -08:00
Jacob Chang
762afcd54a
Merge remote-tracking branch 'origin/master' into jchang_test
2016-12-09 16:56:49 -08:00
Jacob Chang
4c3083c181
Remove unnecessary val
2016-12-09 16:44:30 -08:00
Wesley W. Terpstra
09afbbafdb
ahb: weaken RegisterRouter assertion
...
As written I think it could potentially fail, but what I actually care
about is something weaker that should be true. Assert: nothing lost.
2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
588b944ed4
ahb: implement and test address decoding
2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
5d1064fcb1
ahb: include a unit test
2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
51dfb9cb06
ahb: TileLink master
2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
01b0f6a52b
ahb: new diplomacy-based AHB bus definition
2016-12-08 18:00:39 -08:00
Jacob Chang
54cc071a64
Fix Fragmenter to ensure logical operations must be sent out atomically.
...
Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
2016-12-07 16:22:05 -08:00
Wesley W. Terpstra
c2eedbfe23
tilelink2 Monitor: use Parameters instead of global variables
2016-12-07 12:24:03 -08:00
Wesley W. Terpstra
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
...
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
Andrew Waterman
915697cb09
Fix FEQ flag generation ( #479 )
...
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).
Also, minor code cleanup.
2016-12-06 11:54:29 -08:00
Wesley W. Terpstra
fbfa15efea
TLBroadcast: support non-FIFO devices ( #482 )
2016-12-05 22:10:37 -08:00
Wesley W. Terpstra
3c9718ec8f
clint: undefined registers must be zero ( #480 )
...
This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
2016-12-05 17:11:53 -08:00
Henry Cook
f3d0692619
Make a directory for the config package ( #464 )
...
* [config] make dir structure mirror packages
* [config] expunge max_int
2016-12-05 10:42:16 -08:00
Henry Cook
d0a0c887dc
[tracegen] decrease default address bag size ( #462 )
...
while increasing the default number of requests.
2016-12-04 22:46:55 -08:00
Schuyler Eldridge
36fe024671
CacheName no longer needed in RoCCInterface
...
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
2016-12-04 19:01:39 -08:00
Schuyler Eldridge
624db2034b
Make instantiated RoCC use dcacheParams
2016-12-04 19:01:39 -08:00
Jacob Chang
cff2612cdb
minor Changes needed to support formal tests
2016-12-01 15:02:23 -08:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
e2ec1d00ad
copyright: normalize /// to // in comments
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
a0e10aec05
uncore: removed obsolete Builder file
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
4146f6a792
TLB: do not access illegal addresses ( #460 )
2016-11-26 15:11:42 -08:00
Wesley W. Terpstra
a17753983a
coreplex: allow legacy devices to override the config string ( #458 )
2016-11-25 19:38:24 -08:00
Wesley W. Terpstra
233280e7d2
AsyncBundle: save a wasted bit when depth=1
2016-11-25 18:11:01 -08:00
Wesley W. Terpstra
d755edffcc
DebugTransport: use ToAsyncDebugBus for correct depth
2016-11-25 18:10:28 -08:00
Wesley W. Terpstra
2b80386a9e
rocketchip: TileInterrupts needs a TLCacheEdge ( #456 )
2016-11-25 17:02:29 -08:00
Wesley W. Terpstra
1e0aca7358
dcache: the high bit of s2_req.typ is the SIGN bit (not size) ( #455 )
2016-11-25 15:26:22 -08:00
Wesley W. Terpstra
0baa1c9a45
coreplex: CacheBlockOffsetBits was wrong!
...
This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.
I don't understand how this very serious bug did not cause problems before.
2016-11-24 18:32:44 -08:00
Wesley W. Terpstra
a670f63c81
periphery: a handy trait to turn-off ExtMem
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
30e890b480
diplomacy: include InternalNodes for AXI4 and TL
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
9f1c668c4f
config: when modifying Parameters, subordinate lookups use top
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
566cc9e60b
rocketchip: RTCPeriod config
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
e87f54d4f7
rocketchip: traits for adding external TL2 ports
2016-11-23 20:44:42 -08:00
Wesley W. Terpstra
4b9dc78951
rocketchip: add a parameter-controlled debug port
2016-11-23 15:35:53 -08:00
Henry Cook
38c5af5bad
[rocket] cleanup mshr logic
2016-11-23 12:09:56 -08:00
Henry Cook
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
Henry Cook
c65c255815
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
Wesley W. Terpstra
1d3cad3671
tilelink2 SourceShrinker: handle degenerate cases for free
2016-11-22 22:17:30 -08:00
Wesley W. Terpstra
1e7d597fd3
rocketchip: don't waste too many sources on the AXI master port
2016-11-22 21:48:41 -08:00
Wesley W. Terpstra
c0b27999ea
tilelink2 SourceShrinker: a concurrency reducing adapter
2016-11-22 21:43:38 -08:00
Wesley W. Terpstra
0097274ea3
Broadcast: single-cycle response is possible
2016-11-22 20:45:40 -08:00
Wesley W. Terpstra
437be0f36a
PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool))
...
This results in much less Verilog to simulate
2016-11-22 20:39:38 -08:00
Wesley W. Terpstra
f9de7173cc
PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...))
2016-11-22 18:46:11 -08:00
Wesley W. Terpstra
d9a203b0f0
PositionalMultiQueue: convert 'next' to a single write port
2016-11-22 18:38:55 -08:00
Wesley W. Terpstra
13190a5de0
rocketchip: re-add AXI4 interface
2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
c230580157
coreplex: rename RocketPlex => RocketTiles
2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
bbabcf67ff
coreplex: width adapter should happen as part of coherence manager
...
In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
a140b07009
rocketchip: cut coreplex from rocketchip
2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
c80ee06472
rocketchip: configString is a lazy property of outer
2016-11-22 17:27:58 -08:00
Andrew Waterman
5f3fb64ef0
Per ABI, only x1 and x5 should be treated as function returns
...
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
2016-11-22 12:01:05 -08:00
Wesley W. Terpstra
3d644b943c
coreplex: configString is a property of the RISCVPlatform
2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
e8be365b5d
rocketchip: remove GlobalAddrMap completely
2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
5fe107bb07
rocket: pass scratchpad address to block dcache
2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
c18bc07bbc
TLB: determine RWX from TL2 properties directly
2016-11-21 21:13:26 -08:00
Henry Cook
28c6be90ab
[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
2016-11-20 19:36:51 -08:00
Henry Cook
ff9b5bf8fc
[rocket] nbdcache release bugfix
2016-11-20 19:07:06 -08:00
Henry Cook
3f47d5b5eb
[rocket] re-enable working NBDcache (passes Tracegen)
2016-11-19 19:19:16 -08:00
Henry Cook
c31b41a7ac
[tl2] add grant finisher comment
2016-11-19 19:16:43 -08:00
Colin Schmidt
9dd12545d0
[Rocket] Send correct type for iomshr reqs
...
Also contain grow param bugfix
2016-11-19 19:04:06 -08:00
Wesley W. Terpstra
32a1c27441
rocket: disable nbdcache until it's fully ported
2016-11-18 19:55:24 -08:00
Wesley W. Terpstra
452bb2fc80
dcache fix TinyConfig
2016-11-18 19:50:34 -08:00
Wesley W. Terpstra
d1328a6b6f
rocketchip: remove most uses of GlobalAddrMap
2016-11-18 19:38:02 -08:00
Henry Cook
2976fd84e4
[rocket] resolve cde/config conflicts
2016-11-18 19:11:34 -08:00
Henry Cook
8b908465e0
[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
2016-11-18 19:04:06 -08:00
Henry Cook
5f1cc19d71
[tl2] fix comment explaining permissions
2016-11-18 19:02:17 -08:00
Henry Cook
10112da4e7
[tl2] won't need putthrough opcode
2016-11-18 19:02:17 -08:00
Wesley W. Terpstra
001d9821bd
Merge remote-tracking branch 'origin/master' into tl2-tile
2016-11-18 18:19:41 -08:00
Wesley W. Terpstra
5b594ced29
Plic: support 0 interrupts gracefully
2016-11-18 18:07:44 -08:00
Wesley W. Terpstra
13ec3853ed
junctions: get unit tests running again
2016-11-18 17:38:46 -08:00
Wesley W. Terpstra
10dd6070ad
groundtest: gracefully handle zero uncached ports
2016-11-18 17:26:28 -08:00
Wesley W. Terpstra
03bca77b33
tilelink2 Metadata: cannot assert data good when !valid
2016-11-18 17:16:12 -08:00
Wesley W. Terpstra
be8121eeaf
coreplex: fix clock crossing
2016-11-18 17:15:57 -08:00
Wesley W. Terpstra
0082d713af
coreplex: disable Stateless config until we implement adapter
2016-11-18 16:23:16 -08:00
Wesley W. Terpstra
8059d33217
groundtest: simplify FancyMemtestConfig for now
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
04b9a68ea6
MergedPutRegression: wait for all Puts if tlMaxClientXacts != 3
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
cd19bf65b8
regression: fix bad regression that deadlocks SoC with illegal D stall
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
5f7fa3dae5
regression: remove illegal test which reuses the same ID
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
a6188efc41
rocketchip: break infinite Config loops
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
40daea2e15
util: Config scheme supporting up with ++
2016-11-18 16:18:30 -08:00
Wesley W. Terpstra
e5febcfa33
rocketchip: there are no more useful parameters to dump
2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
30425d1665
rocketchip: eliminate all Knobs
2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
119ccae9af
rocketchip: don't use explicit cde namespace
2016-11-18 14:31:42 -08:00
Richard Xia
bab504cc3f
Add various granular and composable configs.
2016-11-18 11:30:07 -08:00
Henry Cook
5bd343bac8
[rocket] d_last && d.fire() => d_done
2016-11-17 18:42:59 -08:00
Henry Cook
1ddccb1b33
[rocket] add TODO for single cycle ack
2016-11-17 18:42:59 -08:00
Henry Cook
94086f2270
[tl2] broadcast hub probe port width bugfix
2016-11-17 18:42:59 -08:00
Henry Cook
960c2723ab
[tl2] MemoryOpCategories: use def to supply Cat'd consts
2016-11-17 18:42:59 -08:00
Wesley W. Terpstra
179c93db42
tilelink2 broadcast: make it controlled via Config
2016-11-17 17:26:49 -08:00
Wesley W. Terpstra
f4ca5ea1f3
rocketchip: match simulated memory width to ExtMem.beatBytes
2016-11-17 15:40:47 -08:00
Wesley W. Terpstra
12d0d8bea2
rocketchip: remove obsolete bus configuration
2016-11-17 14:30:15 -08:00
Wesley W. Terpstra
c82b371354
rocketchip: remove obsolete TL1 config
2016-11-17 14:24:45 -08:00
Wesley W. Terpstra
dfc3a0dafb
tilelink2: do not depend on obsolete TL1 configuration
2016-11-17 14:07:53 -08:00
Wesley W. Terpstra
8a0ecdaaad
groundtest: ComparatorConfig lives again
2016-11-17 11:07:49 -08:00
Henry Cook
92e233d596
[groundtest] testramaddr constant in package
2016-11-16 18:42:56 -08:00
Henry Cook
e1992d7c55
[rocket] grant addr bugfix
2016-11-16 18:12:06 -08:00
Henry Cook
84f249bd03
[rocketchip] BigInt cast
2016-11-16 18:11:06 -08:00
Henry Cook
da7ecfd189
[rocket] probeack vs probeackdata bugfix
2016-11-16 17:27:02 -08:00
Henry Cook
75d4347192
[groundtest] runs tests with new coreplex and top
2016-11-16 17:05:53 -08:00
Henry Cook
24e3216fcf
coreplex: allow zero interrupt sink/sources
2016-11-16 16:50:36 -08:00
Henry Cook
479bc82f03
tilelink2 Broadcast: improve bufferless throughput
2016-11-16 16:50:36 -08:00
Henry Cook
408e78e35e
rocketchip Periphery: ExtMem and ExtBus Configs
2016-11-16 16:50:30 -08:00
Henry Cook
1f51564577
[rocket] dcache probe ack data bugfix
2016-11-16 14:25:21 -08:00
Henry Cook
66a2c5544e
[rocket] L1D acquire addr bugfix
2016-11-16 13:38:52 -08:00
Henry Cook
c5e03c9c76
[rocket] dcache release addr bugfix
2016-11-16 13:14:51 -08:00
Wesley W. Terpstra
06a7b95d0d
tilelink2 broadcast: support bufferless Config
2016-11-16 12:25:11 -08:00
Wesley W. Terpstra
3703ed39f7
groundtest: PTW needs atomics
2016-11-16 12:16:54 -08:00
Wesley W. Terpstra
5d2e637a4a
tilelink2 Legacy: uncached TL never needs manager_xact_id
2016-11-16 12:16:25 -08:00
Wesley W. Terpstra
10e459fedb
rocket: change connection between rocketchip and coreplex
...
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
Henry Cook
2d68f12115
[tl2] give groundtest tile some output nodes
2016-11-14 18:09:40 -08:00
Wesley W. Terpstra
ab3dafb8bc
Monitor: restore Probe&Acquire checks
2016-11-14 15:36:52 -08:00
Wesley W. Terpstra
385b5d5698
axi4: default should be GET_EFFECTS
2016-11-14 15:19:39 -08:00
Henry Cook
0e30364f56
WIP
2016-11-14 13:39:01 -08:00
Henry Cook
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
Henry Cook
b7730d66f2
WIP bugfixes: run until corrupted WB data (beats repeated)
2016-11-11 18:34:48 -08:00
Henry Cook
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
Henry Cook
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
32fd11935c
rocketchip: use TL2 and AXI4 for memory subsytem
2016-11-04 13:36:47 -07:00
Wesley W. Terpstra
9d77e34bee
tilelink2 Filter: make transfer cap robust against large filters
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
4a2cf6431b
coreplex: make 'mem' port an Option until we can use a Seq
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
8f757a9135
coreplex: rename BankedL2 trait to BankedL2CoherenceManagers
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
b8df59f43b
tilelink2 Broadcast: support "bufferless" implementation
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
14800f8fb4
tilelink2 Broadcast: only support caching readable devices
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
d03046d11c
coreplex: fix BankedL2 line width
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
da3cc3b299
coreplex: TileLink2 l1tol2 memory channels
2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
0f3947bb86
tilelink2 Broadcast: add special case handling for 0 cached clients
2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
ba3c83287f
tilelink2 Xbar: merge the AddressSets of fractured managers
2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
55326c29bb
tilelink2: Filter adapter removes some of the address space
2016-11-03 22:18:23 -07:00
Wesley W. Terpstra
86ba94781b
tilelink2: broadcast coherence manager
2016-11-03 14:37:19 -07:00