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Commit Graph

5182 Commits

Author SHA1 Message Date
f91552a650 Add performance counter support 2016-08-29 12:31:52 -07:00
1e3339e97c Update breakpoints to match @timsifive's debug spec 2016-08-29 12:31:52 -07:00
9ca82dd397 reset default MulDiv config to moderately fast default
Closes #228.

In commit 3f8c60bbd6 I inadvertently
changed the configuration while refactoring it.
2016-08-29 12:31:52 -07:00
33eaf08b60 set missing port direction
Ideally, chisel should flag this as an error.
2016-08-29 12:31:52 -07:00
a19bd6de96 Get in line with FIRRTL randomization flag changes (#231) 2016-08-29 12:29:01 -07:00
35948918b6 Merge pull request #226 from ucb-bar/coreplex_peripheral_interrupts
Allow some External Interrupts to come from Periphery
2016-08-26 11:52:04 -07:00
53ee54dbd1 Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself 2016-08-26 10:40:39 -07:00
41aa80c5d7 Merge remote-tracking branch 'origin/master' into coreplex_peripheral_interrupts 2016-08-26 09:32:36 -07:00
79293f4fa2 Use a better iterator inside the DCache 2016-08-25 20:41:39 -07:00
115e8edd83 Merge branch 'master' into coreplex_peripheral_interrupts 2016-08-25 17:26:56 -07:00
93c801f598 Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227) 2016-08-25 17:26:28 -07:00
abfaae8f4b Merge branch 'master' into coreplex_peripheral_interrupts 2016-08-25 14:57:53 -07:00
4f388add67 More accurate conditional include of generated .d make fragment (#222) 2016-08-25 14:42:04 -07:00
428eed79a1 Allow some External Interrupts to come from Periphery 2016-08-25 14:16:33 -07:00
8ff739d3fa Merge pull request #225 from ucb-bar/remove-openocd
Remove openocd from .gitmodules
2016-08-25 11:01:17 -07:00
3a674b413d Remove openocd from .gitmodules 2016-08-25 10:05:30 -07:00
d5d076200e Merge pull request #213 from ucb-bar/new_test_jtag_DTM
Adds Logic & test support for JTAG implementation of Debug Transport Module.
2016-08-23 18:18:18 -07:00
67467c65f5 Add a jtag-dtm-regression target to the regression
This doesn't get added to Travis, but this target can be used
by other automated testing tools which may want to do further
testing on rocket-chip.
2016-08-23 16:53:50 -07:00
32118269c1 Remove } introduced in merge 2016-08-23 08:20:52 -07:00
c22c77c7a4 remove pointer to openOCD 2016-08-23 07:35:48 -07:00
9974626d6a Merge remote-tracking branch 'origin/master' into HEAD
Conflicts:
	src/main/scala/rocketchip/TestHarness.scala
2016-08-23 07:34:01 -07:00
61aa716f44 fix bus axi connections in periphery 2016-08-22 11:57:15 -07:00
f9ea14b4c2 extra devices should get elaborated in a single build function 2016-08-22 11:57:15 -07:00
96e2cefb34 Merge branch 'master' into HEAD 2016-08-22 11:37:30 -07:00
8d6f080ed0 Merge pull request #215 from ucb-bar/test-harness-fixes
Test harness fixes
2016-08-22 10:33:01 -07:00
b7181ba49b Merge branch 'master' into test-harness-fixes 2016-08-19 22:53:12 -07:00
22ffe36258 Add a queue for timing QoR between L2->MMIO network (#217) 2016-08-19 22:51:49 -07:00
96a868d388 enable the TestDriver to be used in a SystemVerilog UVM-based testbench, which has its own way to manage end-of-simulation and does not like anyone else to call $finish 2016-08-19 17:14:54 -07:00
2d12f6689c make CLOCK_PERIOD actually be the clock period, instead of half of the clock period 2016-08-19 16:55:57 -07:00
4dbcc568dc reorder code to get rid of messy -1 2016-08-19 16:55:57 -07:00
f945acf712 rm race condition on trace_count 2016-08-19 16:55:57 -07:00
75efc7dee7 JtagIO's DRV_TDO should be an INPUT 2016-08-19 16:38:03 -07:00
723cc063cb Move files after the file reorganization 2016-08-19 16:11:41 -07:00
48c5ec3551 add missing jtag file 2016-08-19 16:08:32 -07:00
66a253a0db Remove unncessary file 2016-08-19 16:08:31 -07:00
3dd51ff734 This commit adds Logic & test support for JTAG implementation of Debug Transport Module.
- The DebugTransportModuleJtag is written in Verilog. It probably could be written in
  Chisel except for some negative edge clocking requirement.
- For real implementations, the AsyncDebugBusTo/From is insufficient. This commit
  includes cases where they are used, but because they are not reset asynchronously,
  a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false.
- This commit differs significantly from the earlier attempt. Now, the
  DTM and synchronizer is instantiated within Top, as it is a real piece of
  hardware (vs. test infrastructure).
-TestHarness takes a parameter vs. creating an entirely new TestHarness class.
It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false,
and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM)
is true.

To build Verilog which includes the JtagDTM within Top:

make CONFIG=WithJtagDTM_...

To test using gdb->OpenOCD->jtag_vpi->Verilog:

First, install openocd (included in this commit)

./bootstrap
./configure --prefix=$OPENOCD --enable-jtag-vpi
make
make install

Then to run a simulation:

On a 32-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-e300-sim \
  SimpleRegisterTest.test_s0

On a 64-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-u500-sim \
  SimpleRegisterTest.test_s0
2016-08-19 16:08:31 -07:00
dd4a50c452 Add JTAG DTM and test support in simulation
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
ceff6dd0c8 update README 2016-08-19 13:45:23 -07:00
40bd87bce4 cache the verilator install in travis 2016-08-19 13:45:23 -07:00
1c5034707b fix submodules in regression makefile 2016-08-19 13:45:23 -07:00
f4e0e0966c move rocketchip package sources into its own subdirectory 2016-08-19 13:45:23 -07:00
eba692786b make sure FIRRTL jar gets updated timestamp 2016-08-19 13:45:23 -07:00
7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00
f78da0b0ea add required cloneType methods in non-blocking L1 2016-08-19 13:44:53 -07:00
114226252b Hierarchicalize D$ config 2016-08-19 12:12:34 -07:00
3f8c60bbd6 Hierarchicalize FPU and MulDiv parameters
This gets some leaf-level parameters out of the global parameterization,
better separating concerns.  This commit also allows disabling the
M extension.
2016-08-19 12:06:17 -07:00
fee5d2b1ea Remove parameters for some things that aren't parameterizable
Heads up @colinschmidt and @ccelio.  I'm removing these because
they are ISA constants and so are not truly parameters, so the
parameter place is not the place for them.  Since BOOM and Hwacha
both depend on rocket, you should be able to obtain them by
instantiating/extending rocket.HasCoreParameters.
2016-08-19 12:04:13 -07:00
33676e81f8 use isOneOf as much as possible 2016-08-19 09:56:06 -07:00
d34e790ac0 get rid of duplicated code in rocket Util 2016-08-18 18:40:07 -07:00
7671811ac9 merge uncore.Util into uncore.util 2016-08-18 18:33:46 -07:00