Andrew Waterman
|
4ed2d614a2
|
update to new rocket; retime fpu in dc-syn
|
2012-11-04 16:43:02 -08:00 |
|
Henry Cook
|
538b23c223
|
Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles
|
2012-10-23 12:52:59 -07:00 |
|
Henry Cook
|
17d2bd8926
|
Initial version of sbt tasks (elaborate task with no parameters)
|
2012-10-23 12:52:00 -07:00 |
|
Yunsup Lee
|
3edc1f42aa
|
revamp the backup memory link in the vlsi backend
|
2012-10-23 03:31:34 -07:00 |
|
Andrew Waterman
|
367b5489d1
|
first crack at continuous compilation/testing flow
try it out: cd emulator; make test
|
2012-10-19 04:09:07 -07:00 |
|
Andrew Waterman
|
1ad928cfe2
|
directly integrate dramsim build
also, build it as a static library to simplify dependencies
|
2012-10-18 18:59:37 -07:00 |
|
Andrew Waterman
|
edf0eeed01
|
integrate updated rocket/uncore
|
2012-10-18 17:51:41 -07:00 |
|
Miquel Moreto
|
6d49dc51a0
|
Fixed emulator Makefile + extra info in the README file
|
2012-10-16 11:06:48 -07:00 |
|
Miquel Moreto
|
aa3dc422b4
|
Added first README file
|
2012-10-15 10:54:47 -07:00 |
|
Miquel Moreto
|
5d75ddc553
|
Added dramsim2 memory model to the emulator backend
|
2012-10-14 14:06:28 -07:00 |
|
Yunsup Lee
|
34da073077
|
fix tab
|
2012-10-11 12:09:49 -07:00 |
|
Huy Vo
|
f67f8829e3
|
new rocket + uncore tags, added uncore dependencies to Makefrag
|
2012-10-10 15:44:19 -07:00 |
|
Andrew Waterman
|
7fd4eb6afd
|
update uncore
|
2012-10-09 18:05:32 -07:00 |
|
Andrew Waterman
|
c3236e6ee6
|
add missing symlink and update uncore
|
2012-10-09 17:51:33 -07:00 |
|
Huy Vo
|
24a49350cc
|
reference chip design
|
2012-10-09 13:05:56 -07:00 |
|
Huy Vo
|
93a0182b96
|
everything to get emulator working
|
2012-10-01 19:30:11 -07:00 |
|
Huy Vo
|
8560ea6e40
|
rename hwacha -> riscv-hwacha, chisel, riscv-asm-tests-bmarks, and uncore tags
|
2012-10-01 19:12:18 -07:00 |
|
Huy Vo
|
084a0d31c3
|
initial commit, all the relevant submodules
|
2012-09-26 17:46:17 -07:00 |
|