 Andrew Waterman
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d01e70c672
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decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
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2012-07-17 22:55:40 -07:00 |
|
 Huy Vo
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a79747a062
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
|
 Andrew Waterman
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62a3ea4113
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fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
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Andrew Waterman
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1ebfeeca8a
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
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2012-07-10 05:23:29 -07:00 |
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Huy Vo
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166b857055
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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9b3161920f
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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|
Huy Vo
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6f2f1ba21c
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removing wires
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2012-05-24 10:42:39 -07:00 |
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|
Andrew Waterman
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f804c57bb0
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reduce HTIF clock divider for now
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2012-05-03 04:21:11 -07:00 |
|
 Henry Cook
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00155f4bc4
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Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
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2012-04-24 17:17:42 -07:00 |
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|
Henry Cook
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37eb1a4ae6
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Fixed coherence bug: probe counting for single tile
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2012-04-24 17:17:13 -07:00 |
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|
Andrew Waterman
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98a5d682a5
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coherence mostly works now
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2012-04-10 02:22:45 -07:00 |
|
|
Henry Cook
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1920c97066
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Refactored coherence as member rather than trait. MI and MEI protocols.
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2012-04-10 00:09:58 -07:00 |
|
|
Henry Cook
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5acf1d9820
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defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy
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2012-04-09 23:29:32 -07:00 |
|
|
Henry Cook
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a68f5e016d
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changed coherence type width names to represent max sizes for all protocols
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2012-04-09 23:29:32 -07:00 |
|
|
Henry Cook
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f7307ee411
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changed coherence message type names
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2012-04-09 23:29:31 -07:00 |
|
|
Henry Cook
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d301336c33
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Refactored coherence better from uncore hub, better coherence function names
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2012-04-09 23:29:31 -07:00 |
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|
Andrew Waterman
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257747a3a1
|
no dessert tonight :(
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2012-03-26 23:50:09 -07:00 |
|
|
Andrew Waterman
|
25fe46dc18
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remove bug from dessert
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2012-03-26 14:18:57 -07:00 |
|
|
Andrew Waterman
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4e6302fedc
|
add dessert
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2012-03-25 23:03:20 -07:00 |
|
|
Andrew Waterman
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5a00143035
|
loop host.in to host.out during reset
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2012-03-25 21:45:10 -07:00 |
|
|
Andrew Waterman
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a7ebea13fc
|
add mem serdes unit
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2012-03-25 17:03:58 -07:00 |
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|
Andrew Waterman
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3129040bda
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use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
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2012-03-15 18:36:51 -07:00 |
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Huy Vo
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1b733e7cf0
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-03-13 12:34:39 -07:00 |
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|
Andrew Waterman
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2607153b67
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-03-09 02:08:55 -08:00 |
|
 Yunsup Lee
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4f00bcc760
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-02-29 17:12:02 -08:00 |
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Huy Vo
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0fd777f480
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-02-26 17:24:23 -08:00 |
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|
Andrew Waterman
|
71c8d3fd41
|
reorganize directory structure
|
2012-02-08 15:13:08 -08:00 |
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