Fixed coherence bug: probe counting for single tile
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parent
98a5d682a5
commit
37eb1a4ae6
@ -169,14 +169,16 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.xact_init)
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x_needs_read := co.needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
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if(ntiles > 1) p_rep_count := UFix(ntiles-1)
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val p_req_initial_flags = ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only
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p_req_flags := p_req_initial_flags
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p_req_flags := p_req_initial_flags(ntiles-1,0)
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mem_cnt := UFix(0)
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p_w_mem_cmd_sent := Bool(false)
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x_w_mem_cmd_sent := Bool(false)
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io.pop_x_init := UFix(1) << io.alloc_req.bits.tile_id
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state := Mux(p_req_initial_flags.orR, s_probe, s_mem)
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if(ntiles > 1) {
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p_rep_count := UFix(ntiles-1)
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state := Mux(p_req_initial_flags(ntiles-1,0).orR, s_probe, s_mem)
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} else state := s_mem
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}
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}
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is(s_probe) {
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