In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
* tilelink2 Narrower: support widenening and narrowing on all channels
Be extra careful with the mask transformations
We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.
* tilelink2 SRAM: work around firrtl SeqMem bug
* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)
* tilelink2 mask: fix an issue with width=1 data buses
This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a. The intent was to
fit the dhrystone working set (rofl) which the new value of 40 does.
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
Running rocket-chip through the chisel3 gsdt branch which supports stricter connection checks and uses implicit definitions to deal with "old" direction overrides, exposed a possible bug in the Scala compiler.
[error] .../src/main/scala/uncore/devices/Prci.scala:27: value asOutput is not a member of uncore.devices.PRCIInterrupts{val mtip: chisel3.core.Bool; val msip: chisel3.core.Bool}
[error] possible cause: maybe a semicolon is missing before `value asOutput'?
[error] }.asOutput
[error] ^
[error] one error found
[error] (uncore/compile:compileIncremental) Compilation failed
This change isn't strictly required for current chisel3 code, but is being submitted in anticipation of an eventual merge of the gsdt branch prior to a compiler fix.
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
The previous approach used ex_reg_valid to determine whether to
source data from the FPU or RoCC. Thus, when the RoCC was not
present, it was still creating muxes. Using ex_cp_valid instead
gets rid of them.
- The DebugTransportModuleJtag is written in Verilog. It probably could be written in
Chisel except for some negative edge clocking requirement.
- For real implementations, the AsyncDebugBusTo/From is insufficient. This commit
includes cases where they are used, but because they are not reset asynchronously,
a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false.
- This commit differs significantly from the earlier attempt. Now, the
DTM and synchronizer is instantiated within Top, as it is a real piece of
hardware (vs. test infrastructure).
-TestHarness takes a parameter vs. creating an entirely new TestHarness class.
It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false,
and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM)
is true.
To build Verilog which includes the JtagDTM within Top:
make CONFIG=WithJtagDTM_...
To test using gdb->OpenOCD->jtag_vpi->Verilog:
First, install openocd (included in this commit)
./bootstrap
./configure --prefix=$OPENOCD --enable-jtag-vpi
make
make install
Then to run a simulation:
On a 32-bit core:
$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
--run ./simv-TestHarness-WithJtagDTM_... \
--cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
--freedom-e300-sim \
SimpleRegisterTest.test_s0
On a 64-bit core:
$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
--run ./simv-TestHarness-WithJtagDTM_... \
--cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
--freedom-u500-sim \
SimpleRegisterTest.test_s0
Initial cut
checkpoint which compiles and runs but there is some off-by-1 in the protocol
Debugging the clock crossing logic
checkpoint which works
Clean up the AsyncMailbox black box
