1
0
Commit Graph

1808 Commits

Author SHA1 Message Date
cbe7c51b50 Respect ISA requirements on interrupt priority order
a62e76cb16
2017-08-17 21:27:08 -07:00
e945f6e265 Merge pull request #955 from freechipsproject/fix-acquire-before-release
Fix acquire before release
2017-08-13 18:29:58 -07:00
88332bd885 max-core-cycles: Add a +max-core-cycles PlusArg 2017-08-13 15:47:14 -07:00
3cbc5262ec Don't permit new acquires until the release queue is drained
If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
2017-08-13 13:18:45 -07:00
0190724492 Actually use the C-channel acquire-before-release queue
oops...
2017-08-13 13:03:35 -07:00
7387f2a93a Don't block D-channel when handling a probe
This is an acquire-before-release regression.
2017-08-12 16:13:24 -07:00
604abd5b07 Only report ECC errors when the RAM was actually read 2017-08-12 15:28:03 -07:00
18fb052fc9 DRY 2017-08-12 15:27:30 -07:00
176110b6d3 Don't trigger ECC writebacks when a release is in flight 2017-08-12 15:23:57 -07:00
f191bb994c PatternPusher: can now expect a certain output (#952) 2017-08-11 18:10:27 -07:00
baf769f924 tilelink: add PatternPusher, a device to inject a fixed traffic pattern (#950) 2017-08-11 15:07:10 -07:00
a3358f34a0 Fix priority inversion for two back-to-back divides (#948)
If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit.  While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
2017-08-10 17:12:09 -07:00
0a591c5b5b Roll back use of UIntToOH1 (#946)
These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass.  This is not yet conclusive.
2017-08-09 18:39:47 -07:00
721770244e Fix IBuf bug
Don't examine a packet's xcpt signal if it might be invalid.  In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
2017-08-09 09:47:51 -07:00
a9b1410f01 BusBlocker: parameterize page granularity 2017-08-08 17:10:01 -07:00
010ba94474 BusBlocker: rename a variable 2017-08-08 17:00:22 -07:00
6d6fc38787 BusBlocker: lock bit should affect the prior PMP address, not next 2017-08-08 17:00:12 -07:00
809c7e8551 Don't merge stores that manifest WAW hazards
The following sequence would drop the first store when eccBytes=4:

    sb x0, 0(t0)
    nop
    sb x0, 4(t0)
    nop
    sb x0, 1(t0)

Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
2017-08-08 15:19:05 -07:00
3ef6e4c9f2 Merge pull request #939 from freechipsproject/bus-blocker
tilelink: PMP controlled BusBlocker prevents bus accesses
2017-08-08 15:06:55 -07:00
82e13443b2 Merge pull request #937 from freechipsproject/critical-paths
Perform tag error detectoin/correction in same cycle as RAM
2017-08-08 15:03:28 -07:00
8f261adc6b BusBlocker: change default policy to deny 2017-08-08 14:19:59 -07:00
0d76e96b88 tilelink: PMP controlled BusBlocker prevents bus accesses 2017-08-08 13:28:01 -07:00
7935c61c19 Don't report to the DTIM that data is cacheable
Otherwise, it will attempt to perform AMOs where they're unsupported!
2017-08-08 11:55:04 -07:00
74d309c18e Make I vs. D a static property of TLB, not an input pin
The microarchitecture doesn't really support unified TLBs, so don't fake it.
2017-08-08 11:54:47 -07:00
e92981b0bd DRY 2017-08-08 11:46:38 -07:00
62ccba304c Perform tag error detectoin/correction in same cycle as RAM
The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
2017-08-08 10:21:30 -07:00
6d1d285464 Merge pull request #933 from freechipsproject/cinst
Print out the compressed instruction when executing one
2017-08-07 21:40:10 -07:00
cc1e2af336 Merge pull request #934 from freechipsproject/critical-paths
Revert "Remove one gate from D$ ECC check"
2017-08-07 19:41:08 -07:00
c8f8806df0 Merge pull request #932 from freechipsproject/tl-bus-delayer
tilelink: allow insertion of TLDelayer on TLBus outward node
2017-08-07 19:01:39 -07:00
c4092dd0cc tilelink: improve entropy of bus delayer 2017-08-07 17:36:07 -07:00
402907990c Revert "Remove one gate from D$ ECC check"
This reverts commit 7d94074b05, which
works fine with optimistic behavioral RAMs but not real ones.
2017-08-07 17:33:20 -07:00
2910d6fa2a tilelink: make bus xbar protected so it can be suggestNamed 2017-08-07 17:30:24 -07:00
fc0d5fcf98 Print out the compressed instruction when executing one 2017-08-07 17:21:53 -07:00
e27072e063 Merge pull request #931 from freechipsproject/fix-ram-model-source-reuse
Fix ram model source reuse
2017-08-07 16:56:13 -07:00
c457c9cb9f tilelink: allow insertion of TLDelayer on TLBus outward node 2017-08-07 16:43:06 -07:00
f8b45564d1 tilelink: RAMModel must support source reuse
If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
2017-08-07 16:01:15 -07:00
558fc7f293 maskrom: retain data for d channel is not ready 2017-08-07 12:17:10 -07:00
7fd8bb1159 Merge pull request #928 from freechipsproject/critical-paths
Critical paths
2017-08-06 18:50:59 -07:00
658e36f98b Reduce fanout on frontend io.cpu.req.valid signal 2017-08-06 17:38:51 -07:00
7d94074b05 Remove one gate from D$ ECC check
The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
2017-08-06 17:36:53 -07:00
d03fdc4f30 diplomacy: seal the LazyModuleImpLike trait (#927)
This makes sure that all the base classes call instantiate()
2017-08-06 17:32:23 -07:00
aa60c6944b diplomacy: provide default clock/reset for LazyRawModuleImp 2017-08-06 13:40:07 -07:00
83875e3a0c Only flush D$ on FENCE.I if it won't always be probed on I$ miss 2017-08-05 14:22:40 -07:00
991e16de92 Remove probe address mux from TLB response path 2017-08-05 12:57:38 -07:00
b9b4142bb4 Get s2_nack off the critical path
We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively).  This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
2017-08-05 00:30:36 -07:00
bc298bf146 Optimize ShiftQueue for late-arriving deq.ready 2017-08-04 22:06:37 -07:00
6112adfbb0 Get L2 TLB tag/parity check off the D$ arbitration path 2017-08-04 17:01:51 -07:00
8d97684555 Fix L2 TLB perfctr
It was counting conflict misses but not cold misses.
2017-08-04 17:01:31 -07:00
df7f09b9ce Get I$ ECC check further off critical path 2017-08-04 16:59:21 -07:00
4bfbe75d74 Avoid pipeline replays when fetch queue is full 2017-08-04 16:59:21 -07:00