rocket-chip/src/main/scala at cbe7c51b50112aaa57da9f4e3c41023cf3437968 - rocket-chip - Tiband Gitea

riscv/rocket-chip

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Andrew Waterman cbe7c51b50 Respect ISA requirements on interrupt priority order

https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3

2017-08-17 21:27:08 -07:00

..

tilelink: Error device supports Acquire

2017-07-27 18:32:58 -07:00

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

tilelink: make bus xbar protected so it can be suggestNamed

2017-08-07 17:30:24 -07:00

BusBlocker: parameterize page granularity

2017-08-08 17:10:01 -07:00

diplomacy: seal the LazyModuleImpLike trait (#927 )

2017-08-06 17:32:23 -07:00

chiplink: adjust bus view to include the splitter (#886 )

2017-07-24 21:41:17 -07:00

Use chisel3 Clock() method.

2017-07-07 14:16:39 -07:00

add cloneType to RegisterWriteIO and RegisterReadIO (#874 )

2017-07-18 18:52:31 -07:00

Respect ISA requirements on interrupt priority order

2017-08-17 21:27:08 -07:00

tilelink: add mask rom

2017-07-31 21:34:04 -07:00

Fix priority inversion for two back-to-back divides (#948 )

2017-08-10 17:12:09 -07:00

PatternPusher: can now expect a certain output (#952 )

2017-08-11 18:10:27 -07:00

Combine Coreplex and System Module Hierarchies (#875 )

2017-07-23 08:31:04 -07:00

Optimize ShiftQueue for late-arriving deq.ready

2017-08-04 22:06:37 -07:00