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rocket-chip
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cbe7c51b50
rocket-chip
/
src
/
main
/
scala
History
Andrew Waterman
cbe7c51b50
Respect ISA requirements on interrupt priority order
...
a62e76cb16
2017-08-17 21:27:08 -07:00
..
amba
tilelink: Error device supports Acquire
2017-07-27 18:32:58 -07:00
config
Refactor package hierarchy and remove legacy bus protocol implementations (
#845
)
2017-07-07 10:48:16 -07:00
coreplex
tilelink: make bus xbar protected so it can be suggestNamed
2017-08-07 17:30:24 -07:00
devices
BusBlocker: parameterize page granularity
2017-08-08 17:10:01 -07:00
diplomacy
diplomacy: seal the LazyModuleImpLike trait (
#927
)
2017-08-06 17:32:23 -07:00
groundtest
chiplink: adjust bus view to include the splitter (
#886
)
2017-07-24 21:41:17 -07:00
jtag
Use chisel3 Clock() method.
2017-07-07 14:16:39 -07:00
regmapper
add cloneType to RegisterWriteIO and RegisterReadIO (
#874
)
2017-07-18 18:52:31 -07:00
rocket
Respect ISA requirements on interrupt priority order
2017-08-17 21:27:08 -07:00
system
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
tile
Fix priority inversion for two back-to-back divides (
#948
)
2017-08-10 17:12:09 -07:00
tilelink
PatternPusher: can now expect a certain output (
#952
)
2017-08-11 18:10:27 -07:00
unittest
Combine Coreplex and System Module Hierarchies (
#875
)
2017-07-23 08:31:04 -07:00
util
Optimize ShiftQueue for late-arriving deq.ready
2017-08-04 22:06:37 -07:00