03002b3106
Merge pull request #930 from freechipsproject/fix-maskrom
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maskrom: retain data for d channel is not ready
2017-08-07 16:01:38 -07:00
f8b45564d1
tilelink: RAMModel must support source reuse
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If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
2017-08-07 16:01:15 -07:00
558fc7f293
maskrom: retain data for d channel is not ready
2017-08-07 12:17:10 -07:00
aff028f8f0
Merge pull request #926 from freechipsproject/bump-tools
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bump riscv-tools
2017-08-06 23:04:55 -07:00
3d0051e799
bump tools for test fixes
2017-08-06 22:36:25 -07:00
7fd8bb1159
Merge pull request #928 from freechipsproject/critical-paths
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Critical paths
2017-08-06 18:50:59 -07:00
658e36f98b
Reduce fanout on frontend io.cpu.req.valid signal
2017-08-06 17:38:51 -07:00
7d94074b05
Remove one gate from D$ ECC check
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The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
2017-08-06 17:36:53 -07:00
d03fdc4f30
diplomacy: seal the LazyModuleImpLike trait ( #927 )
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This makes sure that all the base classes call instantiate()
2017-08-06 17:32:23 -07:00
5030a8b15a
Merge pull request #925 from freechipsproject/fix-lazy-raw-modules
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diplomacy: provide default clock/reset for LazyRawModuleImp
2017-08-06 14:42:14 -07:00
aa60c6944b
diplomacy: provide default clock/reset for LazyRawModuleImp
2017-08-06 13:40:07 -07:00
6389120dbd
Merge pull request #923 from freechipsproject/critical-paths
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Critical paths
2017-08-05 17:02:22 -07:00
39b7e930ca
Disable AMBAUnitTestConfig, as it is blocking unrelated PRs
2017-08-05 16:14:02 -07:00
83875e3a0c
Only flush D$ on FENCE.I if it won't always be probed on I$ miss
2017-08-05 14:22:40 -07:00
991e16de92
Remove probe address mux from TLB response path
2017-08-05 12:57:38 -07:00
b9b4142bb4
Get s2_nack off the critical path
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We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively). This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
2017-08-05 00:30:36 -07:00
bc298bf146
Optimize ShiftQueue for late-arriving deq.ready
2017-08-04 22:06:37 -07:00
6112adfbb0
Get L2 TLB tag/parity check off the D$ arbitration path
2017-08-04 17:01:51 -07:00
8d97684555
Fix L2 TLB perfctr
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It was counting conflict misses but not cold misses.
2017-08-04 17:01:31 -07:00
df7f09b9ce
Get I$ ECC check further off critical path
2017-08-04 16:59:21 -07:00
4bfbe75d74
Avoid pipeline replays when fetch queue is full
2017-08-04 16:59:21 -07:00
a45997d03f
Separate I$ parity error from miss signal
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Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
2017-08-04 16:59:21 -07:00
06a831310b
Shave a gate delay off I$ backpressure path
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The deleted code was a holdover from Hwacha's vector fences.
2017-08-04 13:12:43 -07:00
ecc2ee366c
Shave a few gate delays off IBuf control logic
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It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.
2017-08-04 13:12:43 -07:00
82ff81e40d
Merge pull request #924 from freechipsproject/dont-build-debug-verilog
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Don't build verilog twice for emulator and emulator-debug
2017-08-04 10:16:59 -07:00
7937db0c84
Merge pull request #919 from freechipsproject/imiss-perf-counter
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Fix I$ miss perfctr
2017-08-04 01:04:23 -07:00
21ac28b57a
Don't build verilog twice for emulator and emulator-debug
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Since we aren't using chisel2, the output is the same either way.
2017-08-04 01:02:33 -07:00
017ac130c1
Merge pull request #922 from freechipsproject/bigger_tl_xbar
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TLXbar: Allow more masters and slaves and issue a warning.
2017-08-03 16:52:56 -07:00
50c85f1b62
TLXbar: Allow more masters and slaves and issue a warning.
2017-08-03 15:46:06 -07:00
ba4eecc0f0
Use UIntToOH1 ( #921 )
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Closes #920
2017-08-03 14:55:39 -07:00
f483bab4aa
Fix I$ miss perfctr
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The old version was counting prefetches, too.
2017-08-03 00:52:12 -07:00
1be1433f04
Merge pull request #918 from freechipsproject/icache-prefetch
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Icache prefetch
2017-08-02 21:22:20 -07:00
d66e8f8e80
Merge pull request #914 from freechipsproject/critical-paths
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Fix some critical paths
2017-08-02 19:05:31 -07:00
3fc7100048
Merge pull request #917 from freechipsproject/fuzzer_order
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TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
2017-08-02 18:39:59 -07:00
2537d0d54e
Optionally prefetch next I$ line into L2$ on miss
2017-08-02 17:10:56 -07:00
744cdb2f72
Make TLB report when it's safe to prefetch within a page
2017-08-02 17:09:38 -07:00
d9821a74ce
Merge pull request #916 from freechipsproject/transfer_sizes_print
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diplomacy: Pretty Print for TransferSizes
2017-08-02 16:56:36 -07:00
595415d207
TLFuzzer: Correct the number of ordered clients created
2017-08-02 15:48:21 -07:00
fc5c04ed4b
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
2017-08-02 14:44:18 -07:00
7d2dd3769f
Optimize a hazard check critical path
2017-08-02 14:27:25 -07:00
85bdae0fa8
diplomacy: Pretty Print for TransferSizes
2017-08-02 11:40:50 -07:00
2eb239d03f
Add option to retime D$ way mux into subsequent pipeline stage
2017-08-01 23:59:20 -07:00
9464c6db40
Mitigate(?) frontend critical path
2017-08-01 18:51:17 -07:00
735701382f
Mitigate some I$ response valid critical paths
2017-08-01 18:51:17 -07:00
2ecea2ef60
Don't use a pipe queue on D$ TL A-channel
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This cuts an I$->D$ path.
2017-08-01 15:17:07 -07:00
f988b91575
Merge pull request #912 from freechipsproject/add-mask-rom
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tilelink: add mask rom
2017-07-31 22:28:11 -07:00
6ef8ee5d4d
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
4b33249812
Merge pull request #911 from freechipsproject/fix-dcache-bug
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Fix D$ ready-valid signaling bug
2017-07-31 19:14:16 -07:00
42ff74bd34
Merge pull request #910 from freechipsproject/tilelink-map
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Tilelink map
2017-07-31 18:33:09 -07:00
e140893a01
Use 1-entry queue on processor-side E-channel
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The cache can't sink a grant every cycle, so extra E buffering doesn't help.
2017-07-31 18:06:54 -07:00
