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Commit Graph

4505 Commits

Author SHA1 Message Date
Andrew Waterman
ae0716fb6d Use chisel printf for logging 2013-06-13 10:53:23 -07:00
Andrew Waterman
95c5147dc5 Add RISC-V instruction disassembler 2013-06-13 10:31:04 -07:00
Stephen Twigg
bd43ca8423 Merge branch 'master' of github.com:ucb-bar/reference-chip 2013-05-23 17:51:24 -07:00
Henry Cook
c06cbf523b Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore. 2013-05-23 15:26:20 -07:00
Henry Cook
6a69d7d7b5 pass closure to generate bank addr 2013-05-23 14:58:19 -07:00
Henry Cook
9631b6081e Merge branch 'tilelink-data'
Conflicts:
	src/package.scala
2013-05-23 14:53:10 -07:00
Henry Cook
cf02f1ef01 use new locking round robin arbiter 2013-05-23 14:16:50 -07:00
Henry Cook
569d8fd796 Merge branch 'tilelink-data' 2013-05-23 14:14:40 -07:00
Henry Cook
12205b9684 remove obsolete config file reader prototype 2013-05-23 14:09:03 -07:00
Andrew Waterman
fe9adfe71b Simplify and correct integer multiplier 2013-05-22 17:27:50 -07:00
Yunsup Lee
26ed805862 push chisel,riscv-rocket,uncore
linux kernel boots!
2013-05-21 19:00:40 -07:00
Yunsup Lee
11133d6d4c clock gate s2 registers in the frontend 2013-05-21 18:59:21 -07:00
Yunsup Lee
c837c1d800 fix bug in previous JALR commit
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
2013-05-21 18:28:44 -07:00
Henry Cook
69b508ff39 ported caches and htif to use new tilelink 2013-05-21 17:21:04 -07:00
Henry Cook
4c1f105ce9 added PairedData link type with matching crossbar, ported tilelink and uncore to use 2013-05-21 17:19:07 -07:00
Andrew Waterman
28f914c3f2 don't JALR to speculatively-bypassed addresses
Technically not necessary, but probably improves performance.
2013-05-21 16:56:58 -07:00
Yunsup Lee
dcde377303 Fix DM I$ deadlock
BTB predictions were causing infinite miss loops
2013-05-20 15:22:58 -07:00
Andrew Waterman
3a1b5f01b2 don't take interrupts while they're disabled!
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
2013-05-19 23:27:47 -07:00
Andrew Waterman
6eb4c2542a comment out I$ assert for now 2013-05-18 18:09:23 -07:00
Andrew Waterman
1dab984231 use UFix instead of Bits for arithmetic 2013-05-18 00:45:29 -07:00
Andrew Waterman
dfa7a03f73 use assert, not Assert 2013-05-18 00:45:13 -07:00
Yunsup Lee
f3c78abc2b push riscv-tests 2013-05-16 00:51:02 -07:00
Yunsup Lee
e77bde71d0 push riscv-tools 2013-05-15 12:03:52 -07:00
Yunsup Lee
f0b0867f5a push riscv-tests 2013-05-13 19:22:28 -07:00
Yunsup Lee
f13605d2f5 push riscv-tools 2013-05-13 19:14:57 -07:00
Yunsup Lee
7ba3ab03e2 update README 2013-05-13 11:19:55 -07:00
Yunsup Lee
5b55cc93af add submodule riscv-tools 2013-05-10 11:53:55 -07:00
Andrew Waterman
0672773c1a for now, don't use asserts outside of components 2013-05-09 02:14:44 -07:00
Andrew Waterman
e8fcdb56a6 update chisel to work around xilinx ise bug 2013-05-03 01:47:15 -07:00
Andrew Waterman
d825c9d6e9 make fpga Makefile work with updated Makefrag 2013-05-02 05:09:45 -07:00
Andrew Waterman
cfa86dba4f add FPGA test bench
The memory models now support back pressure on the response.
2013-05-02 04:59:32 -07:00
Andrew Waterman
d2e1828714 gracefully kill htif thread, fixing tty stuff 2013-05-02 04:59:32 -07:00
Andrew Waterman
d405ffa949 assume all I$ grants bear data 2013-05-01 21:01:20 -07:00
Henry Cook
9a3b2e7006 new paired meta/data IO type, and matching arbiter 2013-05-01 17:18:12 -07:00
Andrew Waterman
474d321cc7 fix meta hazard counter to reset on new meta writes 2013-05-01 16:35:24 -07:00
Andrew Waterman
a6a88fce19 Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
2013-05-01 16:34:45 -07:00
Andrew Waterman
63a38e7982 Revert "temp"
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
2013-05-01 16:34:33 -07:00
Henry Cook
b6945408cb temp 2013-05-01 10:24:36 -07:00
Henry Cook
722bc917d3 broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle 2013-05-01 10:05:54 -07:00
Yunsup Lee
a86ad08c1e commit awesome vlsi/energy scripts 2013-05-01 02:59:11 -07:00
Andrew Waterman
50bd9a08a7 resynchronize fpga uncore 2013-05-01 01:12:47 -07:00
Henry Cook
9a258e7fb4 use new locking round robin arbiter 2013-04-30 17:10:06 -07:00
Henry Cook
fedc2753e4 make sure master_xact_id field is large enough for temporary extra release trackers 2013-04-30 11:03:34 -07:00
Andrew Waterman
1501e90c1f interlock probe unit on tag RAW hazards 2013-04-30 00:38:22 -07:00
Yunsup Lee
a2f584e928 add riscv-tests, get rid of riscv-asmtests-bmarks 2013-04-29 19:29:51 -07:00
Henry Cook
12d394811e Allow release data to be written out even before all releases have been collected 2013-04-29 18:48:31 -07:00
Henry Cook
e8b20f3d38 clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant 2013-04-25 17:41:04 -07:00
Yunsup Lee
7fe052e1bf update README 2013-04-24 02:05:28 -07:00
Yunsup Lee
9114012def assmebly tests are now built from riscv-tests 2013-04-24 01:59:14 -07:00
Yunsup Lee
93df795e48 change LLC leaf SRAM size 2013-04-22 11:06:50 -07:00