Andrew Waterman
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a94b4af92d
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Simplify AsyncResetRegVec and make AsyncResetReg companion object
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2016-09-16 11:25:10 -07:00 |
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Yunsup Lee
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198a2d7022
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Merge pull request #302 from ucb-bar/tl2-mmio
Tl2 mmio
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2016-09-15 22:45:35 -07:00 |
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Wesley W. Terpstra
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dd19e0911e
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tilelink2: handle bus width=1
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2016-09-15 22:15:11 -07:00 |
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Wesley W. Terpstra
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e1d7f6d7df
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PRCI: always use bus width >= XLen
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2016-09-15 22:15:07 -07:00 |
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Wesley W. Terpstra
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2c53620275
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chisel3: bump for Irrevocable(Decoupled) constructor
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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0e80f7fd0f
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HintHandler: don't violate Irrevocable rules
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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f05222a072
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testconfigs: disable atomics until AtomicAbsorber finished
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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38a9421c75
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Comparator: don't compare addr_beat when it's irrelevant
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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669e3b0d96
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Regression: fix-up address lookup
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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30fa4ea956
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RegisterRouter: compress register mapping for sparse devices
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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6b1c57aedc
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tilelink2: compute minimal decisive mask
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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fb24e847fd
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rocketchip: globals are for sissies
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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644f8fe974
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rocketchip: switch to TL2 mmio + port PRCI
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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91e7da4de3
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tilelink2: make RegisterRouter constructor args public
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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3875e11b26
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tilelink2: RegField splits up big registers
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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5c8e52ca32
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devices: TL2 version of ROM
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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3f30e11f16
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tilelink2: Legacy, manager_xact_id does not matter for uncached
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2016-09-15 21:28:55 -07:00 |
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Wesley W. Terpstra
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ddd93871d8
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tilelink2: add an executable manager parameter
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2016-09-15 21:28:55 -07:00 |
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Wesley W. Terpstra
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9442958d67
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tilelink2: allow := on nodes outside the tilelink2 package
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2016-09-15 21:28:55 -07:00 |
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Jack Koenig
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f2fe437fa4
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Use CDEMatchError for improved performance (#304)
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2016-09-15 19:47:18 -07:00 |
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Henry Cook
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851a336db4
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[unittest] split out Config and TestHarness into separate files, minimize imports
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2016-09-15 14:25:47 -07:00 |
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Henry Cook
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245f8ab76b
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[util] move LatencyPipe into util
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2016-09-15 13:30:34 -07:00 |
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Henry Cook
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a70d8c9821
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Merge remote-tracking branch 'origin/master' into testharness-refactor
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2016-09-15 13:27:07 -07:00 |
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Henry Cook
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be9ddae77f
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make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs
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2016-09-15 13:04:01 -07:00 |
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Henry Cook
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c6f252a913
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Remove Option from success flag in coreplex; just use a sane default.
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2016-09-15 12:19:22 -07:00 |
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Henry Cook
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9e2b0aad65
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Revert "allow MODEL to be something other than TestHarness"
This reverts commit bf253aaa97.
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2016-09-15 11:53:05 -07:00 |
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Henry Cook
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888f6a2a55
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Revert "move UnitTest back into rocketchip module"
This reverts commit f95b8c4ec2.
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2016-09-15 11:48:09 -07:00 |
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Henry Cook
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29ce599ea2
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Merge pull request #295 from ucb-bar/tl2-irrevocable
TL2 -> IrrevocableIO
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2016-09-15 11:33:05 -07:00 |
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Henry Cook
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0a65238920
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Merge branch 'master' into tl2-irrevocable
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2016-09-15 10:30:50 -07:00 |
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Howard Mao
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49863944c4
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merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer
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2016-09-14 21:36:27 -07:00 |
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Howard Mao
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f363f5f709
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wrap TestHarness latency pipe in module
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2016-09-14 21:16:54 -07:00 |
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Howard Mao
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f5db83a72f
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NTiles should not be a Knob
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2016-09-14 21:16:54 -07:00 |
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Howard Mao
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646527c88e
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use named constants to set AXI resp, cache, and prot fields
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2016-09-14 21:16:54 -07:00 |
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Howard Mao
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f95b8c4ec2
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move UnitTest back into rocketchip module
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2016-09-14 20:51:56 -07:00 |
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Howard Mao
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bf253aaa97
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allow MODEL to be something other than TestHarness
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2016-09-14 20:51:56 -07:00 |
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Howard Mao
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8550582f84
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remove redundant verilator rule
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2016-09-14 20:31:17 -07:00 |
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jackkoenig
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a304695ffd
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Add firrtl and verilog Makefile targets to vsim
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2016-09-14 20:29:59 -07:00 |
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Henry Cook
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cde104b3fa
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[junctions] Removes the obsoleted SMI.
Closes #280.
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2016-09-14 20:06:22 -07:00 |
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Yunsup Lee
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96110caca1
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Merge pull request #291 from ucb-bar/move-bootrom
Move BootROM from Coreplex to Periphery
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2016-09-14 19:51:16 -07:00 |
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Henry Cook
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ab3814dcee
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Merge branch 'master' into tl2-irrevocable
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2016-09-14 19:00:17 -07:00 |
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Yunsup Lee
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e404bea2ee
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Merge branch 'master' into move-bootrom
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2016-09-14 18:58:48 -07:00 |
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Yunsup Lee
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f2cb9da91a
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Merge pull request #296 from ucb-bar/split-unittest
refactor unittest framework
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2016-09-14 18:56:11 -07:00 |
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Wesley W. Terpstra
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1c7d7f9d32
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tilelink2 RegisterRouterTest: stall on both edges
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2016-09-14 18:22:12 -07:00 |
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Yunsup Lee
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97809b183f
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refactor unittest framework
as a result, there's another SUITE that needs to run
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2016-09-14 18:10:21 -07:00 |
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Henry Cook
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d35060b881
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[junctions] messed up the merge lulz
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2016-09-14 17:55:16 -07:00 |
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Henry Cook
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1b53e477fa
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Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
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2016-09-14 17:50:17 -07:00 |
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Henry Cook
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e02d149cbe
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Henry Cook
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3030718f72
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bump chisel3
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2016-09-14 17:40:22 -07:00 |
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Henry Cook
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08c4c7b985
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[junctions] make async crossings capable of providing IrrevocableIO
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2016-09-14 17:38:54 -07:00 |
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mwachs5
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ae026edeb3
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Merge pull request #293 from ucb-bar/async_clk_utils
Add some async/clock utilities
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2016-09-14 16:59:27 -07:00 |
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