riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity
3,686 Commits 1 Branch 0 Tags 13 MiB
Commit Graph

3686 Commits

Author SHA1 Message Date
Wesley W. Terpstra c918aa6d89 axi4: name AdapterNode parameters properly 2016-10-12 17:02:02 -07:00
Wesley W. Terpstra a423f97844 axi4: parameterized AXI master constraint for aligned access 2016-10-12 17:02:02 -07:00
Wesley W. Terpstra 673cf1fdb5 tilelink2 ToAXI4: must create irrevocable D for now 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra 8e92ac32b7 tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra 38b6c1c820 tilelink2 axi4: RegisterRouter can cut ready dependency 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra dc26736f32 axi4 tilelink2: include minAlignment and maxAddress in slaves 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra 538437384a tilelink2 Fragmenter: combine AccessAck errors 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra 4caa543ad7 tilelink2: Fragmenter should not cut Acquire parameters 
The correct response to misuse is to fail a requirement check.
Pretending that things are not caches could lead to inconsistency.
 2016-10-11 22:38:03 -07:00
Wesley W. Terpstra 6336f94fa2 tilelink2: only caches can support B requests 2016-10-11 22:38:02 -07:00
Wesley W. Terpstra 4a975ca380 tilelink2: add a rightOR to go with our leftOR 2016-10-11 22:38:02 -07:00
Wesley W. Terpstra b2a5d18e37 diplomacy: simplify address range fragmentation 2016-10-11 22:36:21 -07:00
Wesley W. Terpstra 73e9508c09 Merge pull request #387 from ucb-bar/safer-crossings 
Safer crossings
 2016-10-10 14:44:33 -07:00
Wesley W. Terpstra b0e33f4a39 tilelink2: use TLArbiter in HintHandler 2016-10-10 13:15:28 -07:00
Wesley W. Terpstra 683a2e6785 tilelink2: refactor firstlast helper method 2016-10-10 13:15:28 -07:00
Wesley W. Terpstra a404cd2abf tilelink2: use NodeHandle to restore Crossing.node API 2016-10-10 13:15:28 -07:00
Wesley W. Terpstra 876609eb0e diplomacy: add NodeHandles to support abstraction 2016-10-10 13:15:25 -07:00
Wesley W. Terpstra 97af07eb3e tilelink2: clarify use of Isolation 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra 76388117bb regmapper: detect improper reset sequencing in RegisterCrossing 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra b5f5ef69c1 regmapper: eliminate race condition in RegisterCrossing bypass 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra f250426728 tilelink2: blow up if the channels carry data when they should not 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra 1b09f1360d AsyncQueue: adjust register names to match vals 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra e7f8a7e9ea AsyncQueue: make it clear that the SyncChain is not Gray specific 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra 52b8121e68 Apply "async_queue: Give names to all the registers which show up in the queue (#390)" 
Adjusted to include names for the new registers.
Changes to RegisterCrossing were discarded.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra ffb734ac0e AsyncQueue: disambiguiate the reset_n signal names 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 5ee53c61d6 util: clarify an AsyncQueue corner-case 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 609fd97a71 util: AsyncQueue detect power-down/reset of non-empty queue 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 75bb94017b util: resynchronize AsyncQueue counters when far side resets 
If the other clock domain is much faster than ours, it's reset
might be shorter than a single cycle in our domain. In that case,
we need to catch the reset and extend it.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 5e2609bdd2 AsyncQueueSource: don't feed reset into normal logic! 
There is no need to block writes to mem during reset.
The Queue must be empty anyway.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 2f6985efd3 crossings: use flip not flip() 
This seems to be the more common API
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 6d6aa3eb13 tilelink2: Isolation must also connect reset_n 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra cb7b16f1a9 util: exchange resets between AsyncQueue source and sink 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 8c7d469a95 Revert "async_queue: Give names to all the registers which show up in the queue (#390)" 
This reverts commit a84a961a39.

The changes to RegisterCrossing.scala were unneeded after application of this branch.
The name changes made to the AsyncQueue.scala are reapplied at the end of this branch.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra b6bc6b7a4d Merge pull request #382 from ucb-bar/axi4 
axi4: diplomacy capable AXI4 with TL2 bridge
 2016-10-10 13:11:12 -07:00
Wesley W. Terpstra adf5f1807b tilelink2: ToAXI4 bridge added 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra e856cbe3a6 axi4: SRAM for testing 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra abb02aa6f4 axi4: add a RegisterRouter for generic devices 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra 2f7081aeaf tilelink2: make mask generation reusable 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra b29d34038e axi4: diplomacy capable AXI4 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra dcb9383568 PositionalMultiQueue: work around vcs Lint report 
Lint-[PCTIO-L] Ports coerced to inout
rocket-chip/vsim/generated-src/unittest.UncoreUnitTestConfig.v, 127524
"io_deq_0_valid"
  Port "io_deq_0_valid" declared as output in module "PositionalMultiQueue_16"
  may need to be inout. Coercing to inout.
 2016-10-10 11:21:49 -07:00
Wesley W. Terpstra 5d905a5310 PositionalMultiQueue: shared storage FIFO 1-push n-pop 2016-10-10 11:21:49 -07:00
Andrew Waterman 0af2a5ba02 bump tools 2016-10-09 22:15:55 -07:00
mwachs5 3a1d8fe482 debug: use a different form of the crossing which doesn't create an AsyncScope (#394) 2016-10-09 20:33:18 -07:00
mwachs5 b5d4b72313 register_crossing: Remove the need for AsyncScope by specifying the master clock and reset. (#393) 2016-10-09 15:51:23 -07:00
Henry Cook 1e69a2dc1c [tilelink2] allow TL monitors to be globally enabled or disabled (#392) 2016-10-09 12:34:10 -07:00
Andrew Waterman 53360f4c2c Disable U-mode by default unless S-mode is present 2016-10-08 21:29:40 -07:00
Andrew Waterman 7f429e8799 Simplify AsyncResetReg 
No need for AsyncSetReg, as AsyncResetReg can be used exclusively with
inverted inputs.
 2016-10-08 21:29:40 -07:00
mwachs5 a84a961a39 async_queue: Give names to all the registers which show up in the queue (#390) 
This is to aid debugging but even more so for backend constraint writers, who generally
need predictable names for registers to set false paths, etc.
 2016-10-08 17:50:50 -07:00
Andrew Waterman 4fd03ffdf1 Fix PopCountAtLeast, un-breaking BTB 2016-10-07 21:20:40 -07:00
Howard Mao 5392219d86 bump riscv-tools 2016-10-07 15:50:43 -07:00
mwachs5 4c49fef242 Merge pull request #388 from ucb-bar/cp-safer-crossings 
tilelink2: split isolation gates by direction
 2016-10-07 13:45:23 -07:00