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Commit Graph

234 Commits

Author SHA1 Message Date
ba96ad2b38 Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip 2016-02-27 16:24:45 -08:00
a0f3189c74 Change MIF_DATA_BITS back to 64
It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM.  Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.

Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
2016-02-27 11:43:44 -08:00
9ea8c4e781 Add an 8-channel backup memory port config
Now that the backup memory port works I want to test it.
2016-02-27 10:56:13 -08:00
7319f430d0 Fix the backup memory port on multiple-channel configs
The backup memory port doesn't work on multi-channel configurations, it
just screws up the Nasti tag bits.  This patch always instantiates a
single-channel backup memory port, which relies on the memory channel
selector to only enable a single memory channel when the backup memory
port is enabled.  There are some assertions to make sure this happens,
as otherwise memory gets silently corrupted.

While this is a bit of a hack, the backup memory port will be going away
soon so I don't want to spend a whole lot of time fixing it.  The
generated hardware is actually very similar: we used to elaborate a
Nasti arbiter inside the backup memory support, now there's one outside
of it instead.
2016-02-27 10:47:52 -08:00
7c0c48fac4 Resurrect the backup memory port
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
2016-02-27 10:46:56 -08:00
a2381d2faf RoCC PTW refactoring 2016-02-25 17:26:42 -08:00
ef4915bd2c make the asm suites ordered by their insertion order 2016-02-24 19:49:35 -08:00
ad81d95751 add run-asm-{p,pt,v}-tests targets for convenience 2016-02-24 19:49:35 -08:00
b04cd545b6 pass base SCR address to SCRFile for address calculation 2016-02-24 15:32:46 -08:00
8a877fa620 Add Matthew Naylor's trace generator and AXE scripts 2016-02-24 14:39:11 -08:00
8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00
c263c636b3 Actually reference all the tests from RISCV 2016-02-23 16:05:27 -08:00
bae4c0c0c9 Point Testing to $RISCV/... not $base_dir/...
This uses the compiled tests in RISCV, which match the rest of the toolchain.
2016-02-23 10:58:51 -08:00
4ce603e548 Memtest configs should not have a hex file loaded 2016-02-22 12:49:26 -08:00
0c575403af only use a single asm test and 1 bmark for memtest 2016-02-22 09:36:53 -08:00
5e4a02038c move FPGA AXI to HTIF converter into Chisel module 2016-02-19 13:53:31 -08:00
926efd0cab Allow the number of memory channels to be picked at runtime
We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
2016-02-17 15:23:30 -08:00
db9de94588 Generate and use SCR address header files
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
c1b4d9372f Revert "add new parameters for new SCR file"
This reverts commit 4dad5b8b32.

The commit breaks the build.
2016-02-13 04:02:20 -08:00
6c6bbca92a Revert "use singleton for global"
This reverts commit 4d0f941de3.

The commit breaks the build.
2016-02-13 03:56:47 -08:00
4d0f941de3 use singleton for global 2016-02-13 00:56:11 -08:00
4dad5b8b32 add new parameters for new SCR file 2016-02-12 18:24:12 -08:00
9fb2216548 get rid of unused external mmio port 2016-02-10 21:49:02 -08:00
72a876bfba add NASTI to TL converter 2016-02-10 11:12:39 -08:00
b2ed35e8aa Print a better error on missing config classes
Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.
2016-02-05 09:59:02 -08:00
8422aaf6fc Add a "/" when targetDir doesn't have one
This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.
2016-02-05 09:57:47 -08:00
3bb0f11e6c Chisel3 <> reverse fix 2016-02-05 09:56:42 -08:00
06c3f9b655 Rocket Chip fixes in response to lowRISC team's comments
* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
2016-02-02 13:14:52 -08:00
33aa64212d fix more Chisel3 deprecations 2016-01-14 15:06:30 -08:00
c06884b78c lowercase SMI to Smi 2016-01-11 17:44:10 -08:00
806e40d19b implement DMA streaming functionality 2016-01-07 19:26:15 -08:00
8190bf6e18 implement DMA unit 2015-12-16 21:27:48 -08:00
1a272677ca more fixes to L2 cache 2015-12-16 21:06:39 -08:00
560fdc19a8 add PLRU replacement option to L2 cache 2015-12-16 10:24:57 -08:00
7ad9deeaee Fix issues with request merging in L2 cache and add regression tests
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
2015-12-15 23:02:15 -08:00
0c91e00676 move GroundTest configs to a separate file 2015-12-06 03:01:05 -08:00
4f5dabcda2 add SCR file to device tree 2015-12-05 00:28:58 -08:00
f35b83d3ca allow configuration of rocket ICache buffering 2015-12-02 17:18:39 -08:00
cdc476a370 change Rocc parameterization 2015-12-01 17:56:09 -08:00
e0d849fec5 Fix zscale testing
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
c8c68e75bb base NGenerators on NTiles, not the other way around 2015-12-01 15:26:09 -08:00
40d68406d6 use xlen parameter for ALU 2015-11-30 18:04:44 -08:00
23f0756978 implement support for multiple RoCC accelerators 2015-11-26 12:49:04 -08:00
e25a020e60 Construct device tree ROM in MMIO region
Rebuild riscv-tools for this to work!
2015-11-25 21:23:37 -08:00
ec6bfde9a3 fix WritebackUnit issue in uncore 2015-11-21 16:11:22 -08:00
9d50f37289 fix unused set issue for multiple L2 cache banks 2015-11-20 23:26:28 -08:00
ad3b7fd0e1 adjust CacheFillTest configuration 2015-11-19 10:52:14 -08:00
4806f72b08 add CacheFillTest to check L2 conflict misses 2015-11-19 00:16:28 -08:00
3514b6eb87 add some more useful configurations 2015-11-18 22:11:17 -08:00
379d43d5f4 make MultiChannel routing more performant 2015-11-18 22:11:17 -08:00