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Commit Graph

68 Commits

Author SHA1 Message Date
87a4858aa6 Exit from testbench, not C code
Otherwise, we don't get coverage data from the simulator.
2016-06-23 20:54:07 -07:00
568bfa6c50 Purge legacy HTIF things
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
2d44be747a Fix groundtest without HTIF 2016-06-23 12:17:26 -07:00
30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
4a8e6c773a Fix +verbose flag for verilator 2016-06-17 21:09:08 -07:00
99b257316e replace emulator with verilator for chisel3 2016-06-08 02:43:54 -07:00
50e3caef36 get rid of Zscale file I missed last time 2016-05-31 14:33:38 -07:00
df479d7935 don't make MIFTagBits a computed parameter 2016-05-08 11:04:58 -07:00
487d0b356e fixes to get groundtest working with priv-1.9 changes 2016-05-03 13:09:44 -07:00
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
d0aa4c722d More WIP on new memory map 2016-04-28 16:15:31 -07:00
1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
cf716fea58 fix mm_dramsim2 2016-03-29 20:16:07 -07:00
8c73d10fe1 Support SCR address generation with __OFFSET at the end 2016-02-25 21:57:37 -08:00
a073c37e36 The FPGA doesn't have an HTIF clock divider
We used to just be writing the SCR anyway, but now that the SCR maps are
automatically defined VCS will detect the missing SCR and bail out when
compiling test harness code.  This patch just doesn't write the HTIF SCR when
there isn't one.
2016-02-22 16:15:07 -08:00
926efd0cab Allow the number of memory channels to be picked at runtime
We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
2016-02-17 15:23:30 -08:00
db9de94588 Generate and use SCR address header files
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
6fc1e92708 add option to print cycle count regardless of exit status 2015-12-04 12:04:13 -08:00
e0d849fec5 Fix zscale testing
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
ba5a6af05c correctly stripe data across memory channels in simulation 2015-11-05 10:48:32 -08:00
dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
c517d9f6e3 fix htif emulator constructor in vcs_main 2015-09-25 17:21:09 -07:00
5e3f9115d3 make sure HTIF mem_mb doesn't exceed MMIOBase 2015-09-25 09:02:35 -07:00
f200d0947a Force C++ emulator to always use 1GB for MEM_SIZE
Fixes #17
2015-09-24 23:56:41 -04:00
fbc6e695d3 remove bugs from float_fix 2015-09-23 16:11:47 -07:00
56daea793a allow float_fix to take stdin (for piping) 2015-09-23 16:09:09 -07:00
38a9b23ce7 add a flag to only log and dump after a certain number of cycles 2015-09-22 10:32:31 -07:00
4496e8d4e2 make sure htif_emulator properly sets memory size 2015-09-22 10:32:31 -07:00
de81762f7c faster and more conservative float_fix 2015-09-15 17:19:29 -07:00
7e25b1ce03 cleaner/faster comlog without linear search 2015-09-15 17:19:29 -07:00
3eed7ff238 make float_fix more conservative with replacement 2015-09-12 11:00:00 -07:00
a12cd13190 tool to unrecode single floats from commit logs 2015-09-11 20:19:18 -07:00
c8a7deb950 Added a commitlog post-processor for Rocket
- Useful for taking Rocket's out-of-order writebacks and generating an
    in-order commit log.
  - Resulting commit log can be diffed against Spike's commit log.
2015-09-11 16:06:01 -07:00
0ac6172525 Add "-memsize" flag to emulator
- Allow user to set memory size (in MiB) used by emulator.
   - if memory is exhausted, warn user about memory shortage.

Close #3
2015-08-26 17:53:37 -07:00
d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
1cfd9f5a0e add LICENSE 2014-09-12 10:15:04 -07:00
275b72368b add CONFIG to the name of simulator executable 2014-09-11 22:11:58 -07:00
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
d2c32b048a fix bug in htif_fini, need to use vc_handle! 2014-03-18 01:35:08 -07:00
0d124d283a Write our own vcs main() routine 2014-03-17 17:02:28 -07:00
7f23257873 Print out random seed if test fails 2014-03-17 15:35:32 -07:00
d055c0ebaf Push rocket/hardfloat/chisel 2014-03-04 16:39:06 -08:00
dfc13236d1 Linux works again! 2014-01-16 12:44:29 -08:00
ab6cd9c9e8 Update chisel, rocket 2013-12-09 15:09:48 -08:00
c55eee7244 Pass target machine exit code back to host OS 2013-10-29 13:24:09 -07:00
fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00