Jim Lawson
907d369bde
Remove tests obsoleted by new FP encoding proposal ( #672 )
2017-04-11 19:12:35 -07:00
Wesley W. Terpstra
1c36ab8bf7
Fragmenter: forbid multiple sink IDs
...
Otherwise a slave might respond with different IDs for different
requests and the Fragmenter would violate the requirement that
control signals remain unchanged for a burst.
2017-04-11 12:38:00 -07:00
Wesley W. Terpstra
84dc2ae822
CacheCork: remove probe support
2017-04-11 12:34:18 -07:00
Andrew Waterman
9a983c12a3
Implement new FP encoding proposal
...
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
2017-04-10 22:38:25 -07:00
Andrew Waterman
470c6711a7
Do some CSE by hand, per @terpstra
2017-04-10 22:38:25 -07:00
Wesley W. Terpstra
71bf929505
maskgen: support wider granularity result ( #665 )
...
Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
2017-04-09 20:06:23 -07:00
Andrew Waterman
a43bf2feae
Add vectored interrupt support
...
4dcaa944ba
I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:
ba6d88466a
2017-04-08 00:29:45 -07:00
Megan Wachs
051acee76c
Debug: Fix off-by-1 for detecting nonexistent harts.
2017-04-07 16:47:16 -07:00
Megan Wachs
01372e1686
use Wire() correctly to assign a value
2017-04-07 16:47:16 -07:00
Megan Wachs
9ae4838708
jtag: Get rid of chisel deprecation warnings
2017-04-07 16:47:16 -07:00
Megan Wachs
22c6f728c3
debug: Use flags for resume instead of program buffer. Untested.
2017-04-07 16:47:16 -07:00
Megan Wachs
d361e9e343
debug: temporarily leave preexec in place
2017-04-07 16:47:16 -07:00
Megan Wachs
0e2c34b0d6
debug: update register map with new spec
2017-04-07 16:47:16 -07:00
Megan Wachs
df5caba7bf
debug: Make it easier to override parts of the Default Debug Config ( #655 )
...
* Handle single-step with a pipeline stall, not a flush
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
* debug: Make it easier to override parts of the Default Debug Config
* Fix typo in Debug code generation
abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
2017-04-06 10:33:17 -07:00
Andrew Waterman
c861c4925e
Don't signal access exceptions on invalid PTEs
...
The PPN should not be interpreted in this case.
2017-04-05 21:46:55 -07:00
Andrew Waterman
2e09253d26
Revive I$ parity option
...
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
2017-04-05 21:46:55 -07:00
Andrew Waterman
43917dd59f
Get I$ s1_kill signal off the critical path
2017-04-05 21:46:55 -07:00
Andrew Waterman
744fb2e4b9
Cut imem.resp.ready critical path with a flow queue
...
This is only necessary for RVC, where the decode latency is much higher.
2017-04-05 21:46:55 -07:00
Andrew Waterman
3e72f9779f
Handle single-step with a pipeline stall, not a flush
...
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
2017-04-05 19:52:44 -07:00
Megan Wachs
2601740542
debug: fix some typos related to the ID->SEL mapping functions
2017-04-05 15:14:32 -07:00
Megan Wachs
b94f1f15b0
debug: redirect DMI NOPs to CONTROL register so things don't hang during reset
2017-04-05 15:14:32 -07:00
Megan Wachs
eef05cc1fc
debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes.
2017-04-05 15:14:32 -07:00
solomatnikov
127f121ef2
Preserve id_do_fence ( #651 )
2017-04-05 08:29:45 -07:00
Andrew Waterman
19f0ae64a0
Only set id_reg_fence when AMO/FENCE is actually executed
...
This is a performance bug, not a correctness bug. But randomly stalling
because of garbage bits coming out of the I$ should be avoided.
h/t @solomatnikov
2017-04-03 21:13:52 -07:00
Megan Wachs
629e9a2ef6
debug: Put DebugROM back inside the overall Debug Module ( #647 )
2017-04-03 16:36:53 -07:00
Megan Wachs
d2c1bdc2ce
Debug Controls ( #639 )
...
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.
* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
2017-04-03 13:31:35 -07:00
Andrew Waterman
410e9cf736
I$ bugfix, to be reworked
2017-03-31 12:17:41 -07:00
Henry Cook
b9550e8523
Merge branch 'master' into name-rams
2017-03-30 17:36:01 -07:00
Andrew Waterman
a8a2ee711c
Give I$ RAMs consistent names
2017-03-30 15:50:54 -07:00
Andrew Waterman
2720095b8e
Give D$ RAMs consistent names
2017-03-30 15:49:14 -07:00
Andrew Waterman
70e7e90c02
Remove splitMetadata option from L1 caches
...
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
2017-03-30 15:48:55 -07:00
Megan Wachs
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
Andrew Waterman
fd39eadcd6
New PMP encoding
2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
2f2b472098
rocket: split the interrupt controller into its own node
2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
a2fc51d65e
soc: compatible with "simple-bus" => scanned for platform devices
2017-03-30 00:36:23 -07:00
Andrew Waterman
3546c8d133
If any PMPs are supported, all CSRs exist
2017-03-30 00:36:23 -07:00
Andrew Waterman
8f73a58d90
Report access exception, not page fault, if page-table walk fails
2017-03-30 00:36:23 -07:00
Andrew Waterman
25232070ec
Don't redundantly set resp_ae in PTW
2017-03-30 00:36:23 -07:00
Andrew Waterman
80fb002962
Don't use Vec as lvalue
2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253
get local interrupts out of the tile
2017-03-30 00:36:23 -07:00
solomatnikov
0b9fc94421
Assertion for back-to-back uncached and cached ops ( #631 )
2017-03-29 23:07:17 -07:00
Megan Wachs
d8033b20fc
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-29 14:58:04 -07:00
Megan Wachs
375a039279
debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec)
2017-03-28 21:14:22 -07:00
Megan Wachs
ca9a5a1cf7
debug: Fixes in how the SimDTM was hooked up to FESVR
2017-03-28 21:13:45 -07:00
Andrew Waterman
8dfbf4532a
Use 1 MHz as default timebase ( #628 )
...
Defaulting to 0 prevents Linux from booting
2017-03-28 19:59:56 -07:00
Andrew Waterman
44fb3be7d0
Fix MMIO/cache refill concurrency bug in DCache
...
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
2017-03-28 17:16:29 -07:00
Andrew Waterman
db3ed12ce3
Fix regression in groundtest DummyPTW
...
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
2017-03-28 00:56:14 -07:00
Andrew Waterman
4215f480ef
Write instruction to badaddr on illegal instruction traps
2017-03-28 00:56:14 -07:00
Megan Wachs
d6ab929c41
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
Megan Wachs
bb64c92906
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
Megan Wachs
42ca597478
debug: Breaking change until FESVR is updated as well.
...
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
Megan Wachs
43804726ac
tilelink2: more helpful requirement message
2017-03-27 21:05:05 -07:00
Megan Wachs
0c3d85b52b
debug: add generated ROM contents and register fields.
2017-03-27 21:01:36 -07:00
Andrew Waterman
05cbdced78
Work around zero-entry vec issue in Chisel
2017-03-27 17:57:26 -07:00
Andrew Waterman
d42d8aaea7
Make SEIP writable
2017-03-27 16:37:09 -07:00
Andrew Waterman
c7c357e716
Add local interrupts to core (but not yet to coreplex)
2017-03-27 16:37:09 -07:00
Andrew Waterman
069858a20c
rocket: separate page faults from physical memory access exceptions
2017-03-27 16:37:09 -07:00
Andrew Waterman
ea0714bfcb
rocket: hard-wire UXL/SXL fields to 0
...
a2a3346e73
2017-03-27 16:37:09 -07:00
Wesley W. Terpstra
5b339b6bbd
tilelink2 Monitor: catch incorrect use of source ID
2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
75eba294ec
DCache: Release from the correct ID as well
2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
4959771c97
Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N"
...
This reverts commit 0538dc77ce
.
2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
fa7ead6357
Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO"
...
This reverts commit fb6498f2c3
.
2017-03-27 16:30:46 -07:00
Megan Wachs
70fa10fc55
Util: Add ResetCatchAndSync for synchronous deassert of Async Reset ( #615 )
2017-03-27 03:29:07 -07:00
Megan Wachs
08c4f7cea6
RocketTile: Create a wrapper for SyncRocketTile as well ( #616 )
...
* RocketTile: Create a wrapper for SyncRocketTile as well
There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.
Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.
Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.
It could still be nice to use a parameter vs hard coding "3".
* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
Megan Wachs
11507ac7d6
TLROM: Use Resource as a parameter rather than assuming SimpleDevice.
...
This allows more flexibility e.g. considering the ROM as part of other
devices.
2017-03-26 20:58:14 -07:00
Megan Wachs
bf648514e3
TLROM: allow name and compatibility strings to be provided by subclasses.
2017-03-26 20:58:14 -07:00
Megan Wachs
8e6beb80be
Add ucb-art/chisel-jtag ( #612 )
...
* jtag: Add ucb-art/chisel-jtag to junctions.
* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch
* jtag: move to a top-level package
2017-03-26 18:03:21 -07:00
Andrew Waterman
0e2b780089
Bump hardfloat, giving us the 5th rounding mode finally!
2017-03-26 14:20:16 -07:00
Andrew Waterman
e710e32f10
Implement new FP encoding proposal
...
Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
2017-03-26 14:20:16 -07:00
Andrew Waterman
7180352067
Fix groundtest to provide missing signals to TLB
2017-03-26 14:20:16 -07:00
Andrew Waterman
5d1165c850
Express PMP mask generator using a carry chain
...
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
2017-03-26 14:20:16 -07:00
Andrew Waterman
bb42f3bf3b
WIP on FPU subword recoding
2017-03-26 14:20:16 -07:00
Wesley W. Terpstra
537274b645
coreplex: move buffers inside the coreplex
...
This should make hierarchical place and route easier.
2017-03-24 22:54:48 -07:00
Yunsup Lee
5bbb75e078
rename l2FrontendBus as fsb, expose bsb
2017-03-24 22:54:48 -07:00
Henry Cook
996a31364a
rocket: remove hard-coded paddrBits ( #610 )
...
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
Wesley W. Terpstra
f36b1766f8
TLROM: use the smallest ROM implementation that works
...
The contents everywhere else are still zero.
2017-03-24 20:40:28 -07:00
Wesley W. Terpstra
ac205ca10a
bootrom: move to 0x10000 for more space (DTB on multicore is big)
2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
34f8ce653a
bootrom: follow SBI (a0=hartid, a1=dtb)
2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
9a2f0d01a1
GenerateBootROM: use compiled DTB
2017-03-24 18:18:01 -07:00
Andrew Waterman
17b1ee3037
Default to 8 PMPs; support 0 PMPs
2017-03-24 16:39:52 -07:00
Andrew Waterman
97006ab396
Don't modulate PMP privilege on passsthrough when !usingVM
2017-03-24 16:39:52 -07:00
Andrew Waterman
3f0d2fe826
Instantiate PTW unconditionally
...
This keeps the PMP datapaths intact. The PTW itself will get optimized
away for the !usingVM case.
2017-03-24 16:39:52 -07:00
Andrew Waterman
30415215b8
Don't check for exceptions on ScratchpadSlavePort accesses
2017-03-24 16:39:52 -07:00
Andrew Waterman
ccd5bc9a91
Improve QoR of PMP homogeneity checker
2017-03-24 16:39:52 -07:00
Andrew Waterman
e9cadf29d2
Improve DCache MMIO QoR
...
No need to store the cmd field. From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
2017-03-24 16:39:52 -07:00
Andrew Waterman
fb6498f2c3
Use Reg(Vec) instead of Seq(Reg) for DCache MMIO
2017-03-24 16:39:52 -07:00
Andrew Waterman
0538dc77ce
For D$, use source 0 through N-1 for MMIO, not 1 through N
...
This makes the code a bit cleaner.
2017-03-24 16:39:52 -07:00
Andrew Waterman
3951e57789
Force each TLB entry into its own clock-gate group
...
This ameliorates a PMP critical path.
I can't figure out how to do this without asUInt/asTypeOf.
2017-03-24 16:39:52 -07:00
Andrew Waterman
8d7f1d777e
Fix an embarrassing typo in the PMPHeterogeneityChecker
2017-03-24 16:39:52 -07:00
Andrew Waterman
10c39cb8d6
Disable mprv in D-mode
2017-03-24 16:39:52 -07:00
Andrew Waterman
d3bda9574c
Put page homogeneity checker in PMP
...
Avoids redundancy between ITLB and DTLB
2017-03-24 16:39:52 -07:00
Andrew Waterman
9e05200e51
Don't require that PMP ranges be aligned to access size
...
e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
2017-03-24 16:39:52 -07:00
Andrew Waterman
29e67279ba
add comments
2017-03-24 16:39:52 -07:00
Andrew Waterman
4c8be13a4d
Improve homogeneity circuit QoR
2017-03-24 16:39:52 -07:00
Andrew Waterman
59d6afa132
mideleg/medeleg not present without less-privileged traps
2017-03-24 16:39:52 -07:00
Andrew Waterman
38808f55d5
Share PMP mask gen between I$ and D$
2017-03-24 16:39:52 -07:00
Andrew Waterman
86d84959cf
More WIP on PMP
2017-03-24 16:39:52 -07:00
Andrew Waterman
2888779422
Flush pipeline from WB stage, not MEM
...
Fixes sptbr write -> instruction translation hazard.
2017-03-24 16:39:52 -07:00
Andrew Waterman
44ca3b60ab
Retime PTW response valid bits
...
It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
2017-03-24 16:39:52 -07:00
Andrew Waterman
a03556220c
Default TLB size = 32
...
@davidbiancolin
2017-03-24 16:39:52 -07:00
Andrew Waterman
1875407316
Get TLB permission checks off D$ clock gating critical path
2017-03-24 16:39:52 -07:00
Andrew Waterman
a4164348b4
Expose MXR to S-mode
2017-03-24 16:39:52 -07:00
Andrew Waterman
0380aed329
PUM -> SUM
2017-03-24 16:39:52 -07:00
Andrew Waterman
2a413e4496
Remove fruitless debug()
2017-03-24 16:39:52 -07:00
Andrew Waterman
29414f3a23
Simplify interrupt-stack discipline
...
f2ed45b179
2017-03-24 16:39:52 -07:00
Andrew Waterman
723352c3e2
Mitigate some more PMP critical paths
2017-03-24 16:39:52 -07:00
Andrew Waterman
7484f27ed3
Don't gate exception-cause pipeline registers separately
...
They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
2017-03-24 16:39:52 -07:00
Andrew Waterman
3ea822c2cf
Make blocking L1 D$ the default
...
The nonblocking cache is overdesigned for most Rocket-class cores, so
the blocking cache is the more appropriate default.
2017-03-24 16:39:52 -07:00
Andrew Waterman
487b8db5ef
Address some PMP critical paths
2017-03-24 16:39:52 -07:00
Andrew Waterman
03fb334c4c
Take mprv calculation off critical path
2017-03-24 16:39:52 -07:00
Andrew Waterman
f0796f0509
Pass correct access size information to PMP checker
2017-03-24 16:39:52 -07:00
Andrew Waterman
a6874c03f7
Remove DecoupledTLB
2017-03-24 16:39:52 -07:00
Andrew Waterman
78f9f6b9ef
When SFENCE.VMA has rs2 != x0, don't flush global mappings
2017-03-24 16:39:52 -07:00
Andrew Waterman
1b950128e1
PTW should always use S-mode privilege
...
If an exception occurs while a page-table walk is coincidentally in
progress (e.g., an illegal instruction executes during data TLB refill),
then the processor might enter M-mode. However, the PTW's accesses
should proceed without M privilege, to avoid bypassing PMPs.
Note, the same argument doesn't apply to the nonblocking cache's replay
queues, because those accesses have already been checked against the PMPs.
The cache correctly ignores access exceptions reported on replays,
provided no exceptions were reported on the initial access.
2017-03-24 16:39:52 -07:00
Andrew Waterman
aace526857
WIP on PMP
2017-03-24 16:39:52 -07:00
Andrew Waterman
b1b405404d
Set PRV=M when entering debug mode
...
Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
2017-03-24 16:39:52 -07:00
Andrew Waterman
cf168e419b
Support SFENCE.VMA rs1 argument
...
This one's a little invasive. To flush a specific entry from the TLB, you
need to reuse its CAM port. Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.
This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation). It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
2017-03-24 16:39:52 -07:00
Henry Cook
797c18b8db
Make some requirement failures more verbose ( #608 )
...
* tilelink: verbose requires in xbar
* diplomacy: verbose requires
2017-03-23 21:55:11 -07:00
Wesley W. Terpstra
bd08f10816
tilelink2: make sink ids optional ( #607 )
...
* tilelink2: make sink ids optional
* CacheCork: add a special-case for 1 sink id
2017-03-23 18:19:04 -07:00
Wesley W. Terpstra
19eb9b6906
l1tol2: put a flow Q on the exits ( #606 )
...
This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
2017-03-23 16:28:32 -07:00
Henry Cook
055b8ba1f0
rocket: avoid LinkedHashMap.keys to preserve traversal order ( #603 )
2017-03-22 14:38:33 -07:00
Andrew Waterman
76f083b469
FIFOFixer: Not all D-channel messages are A-channel responses
2017-03-21 14:17:38 -07:00
Andrew Waterman
3609254e4a
There's no structural hazard on MMIO store responses
...
So don't stall as though there were.
2017-03-21 14:17:32 -07:00
Yunsup Lee
5eae7e1da4
make DCache s1_nack less conservative for pipelined MMIO requests
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
4c00066746
rocket: describe dcache as two clients (fifo+cached)
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
81d717e82f
coreplex: guarantee FIFO for those tiles that need it
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
198afddb4b
tilelink2: add the FIFOFixer
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
c33f31dd3c
tilelink2 RAMModel: weaken fifo requirement check
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
930438adba
tilelink2 SourceShrinker: destroy FIFO behaviour
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
fd521c56a6
tilelink2: add client-side FIFO parameterization
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
4eef317e84
RegisterRouter: support devices with gaps
2017-03-20 14:49:22 -07:00
Wesley W. Terpstra
431cb41e27
tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E
2017-03-20 14:49:22 -07:00
Wesley W. Terpstra
04892fea01
Monitor: support early ack
2017-03-20 14:49:19 -07:00
Wesley W. Terpstra
278f6fea24
tilelink2: define is{Request,Response} based on spec
2017-03-20 13:41:02 -07:00
Wesley W. Terpstra
778e189bba
Monitor: ProbeAckData and ReleaseData may carry an error
2017-03-20 11:44:13 -07:00
Wesley W. Terpstra
48c7aed4e1
Monitor: any probe supported by the client is legal
2017-03-20 11:34:19 -07:00
Wesley W. Terpstra
0c92283a61
rocket icache: tie off b ready
2017-03-19 17:18:50 -07:00
Wesley W. Terpstra
c9459fe4eb
tilelink2 Xbar: don't use unnecessary ports
2017-03-19 17:02:24 -07:00
Wesley W. Terpstra
7971947d6c
tilelink2 Monitor: don't inspect bits if valid is forbidden
2017-03-19 16:34:23 -07:00
Wesley W. Terpstra
a4ca424a22
AHBToTL: finally get the error signal right? ( #594 )
2017-03-18 22:24:20 -07:00
Wesley W. Terpstra
f6daa782d3
AHBToTL: fix the order of updates to d_pause ( #592 )
2017-03-17 19:34:40 -07:00
Megan Wachs
dcc9827ab4
Rename Prci.scala to Clint.scala ( #591 )
...
The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.
2017-03-17 15:36:10 -07:00
Wesley W. Terpstra
db55a1d755
Fragmenter: fix a bug when underlying device supports larger bursts ( #589 )
2017-03-17 11:00:49 -07:00
Wesley W. Terpstra
9b5b3279a6
AHBToTL: don't report error during idle cycles
2017-03-16 18:18:29 -07:00
Wesley W. Terpstra
5efd38bf97
apb: put both aFlow options under regression
2017-03-16 15:36:14 -07:00
Wesley W. Terpstra
882a7ff8ff
TLToAPB: use the now standard aFlow parameter name
2017-03-16 15:34:59 -07:00
Wesley W. Terpstra
e31b84af33
axi4: use common BufferParams
2017-03-16 15:32:17 -07:00
Wesley W. Terpstra
ca2c709d29
TLBuffer: move TLBufferParams to diplomacy.BufferParams
2017-03-16 15:19:36 -07:00
Wesley W. Terpstra
778c8a5c97
ToAHB: appease AHB VIP
2017-03-16 15:17:05 -07:00
Wesley W. Terpstra
963d244094
unittest: try both aFlow settings of TLToAHB
2017-03-16 15:13:57 -07:00
Wesley W. Terpstra
604a164b97
TLToAHB: rename parameter to aFlow
2017-03-16 15:10:54 -07:00
Wesley W. Terpstra
bb49575368
ahb: rewrote TLToAHB to avoid retracting requests on stall
2017-03-16 14:36:30 -07:00
Wesley W. Terpstra
c95c2ca9c8
AHB: include bridge unit tests
2017-03-14 18:34:21 -07:00
Wesley W. Terpstra
0c5fd76089
ahb: implement a ToTL bridge
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
7f71df0925
apb: better test coverage
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
5885bf29b5
axi4: improve test harness
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
d98fd942f1
tilelink2: optimize the supportsX check circuits
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
3c5c877409
tilelink2: make TLBuffer API more flexible
2017-03-14 14:06:18 -07:00
Wesley W. Terpstra
6fc3ec3d63
tileink2: add a TestRAM; a zero-delay RAM useful for testing
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TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
2017-03-14 14:06:17 -07:00
Henry Cook
bb0390630c
Merge branch 'master' into priv-1.10
2017-03-13 21:40:12 -07:00
Leway Colin
1322a02637
Fixed Hasti can't handle N masters to one slave #571 ( #576 )
2017-03-13 20:36:53 -07:00
Andrew Waterman
d6f571cbbb
Implement mstatus.TSR
2017-03-13 14:50:06 -07:00
Andrew Waterman
1fea0460ba
Support superpage entries in TLB
2017-03-13 14:50:06 -07:00
Andrew Waterman
2d267b4940
Support corner cases in TLBPermissions
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Don't crap out if the yes-set or no-set is empty.
2017-03-13 14:50:06 -07:00
Andrew Waterman
90b5cc96cb
Gracefully handle empty ports in AddressDecoder
2017-03-13 14:50:06 -07:00
Wesley W. Terpstra
c847559853
TLB: add a helper API to determine homogeneous page permissions
2017-03-13 14:50:06 -07:00
Wesley W. Terpstra
eaf474a081
LFSR: use random intial value of the start register
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We just need to make sure it doesn't initialize randomly stuck at 0.
2017-03-13 13:17:52 -07:00
Henry Cook
1a3fec61c0
Merge branch 'master' into priv-1.10
2017-03-13 11:59:18 -07:00
Wesley W. Terpstra
d2da33e4b1
Fuzzer: use different LFSR seeds based on simulator seed
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
bb6108abd5
Tests: include more random delays
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
0c7fb87390
TLDelayer: insert noise on invalid cycles
2017-03-11 02:53:43 -08:00
Jacob Chang
1c6dde8c15
Make parameters for TLToAHB and TLToAXI4 accessable ( #581 )
2017-03-10 22:26:38 -08:00
Henry Cook
dbc8f4b30b
last => done
2017-03-10 15:58:38 -08:00
Andrew Waterman
380c10f7bd
Zap conflicting TLB entries, preparing for superpage support
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Superpages create the possibility that two entries in the TLB may match.
This corresponds to a software bug, but we can't return complete garbage;
we must return either the old translation or the new translation. This
isn't compatible with the Mux1H approach. So, flush the TLB and report
a miss on duplicate entries.
2017-03-10 15:58:23 -08:00
Andrew Waterman
b24c43badb
Don't double-count release traffic in perfctrs
2017-03-09 16:49:02 -08:00
Andrew Waterman
63f8ce36f6
Avoid VM exceptions in groundtest by setting Accessed bit
2017-03-09 16:48:28 -08:00
Andrew Waterman
4f8f05d635
Add performance counter facility
2017-03-09 13:58:50 -08:00
Andrew Waterman
33b6d48376
Fix haltnot reporting (previously always returned 0)
2017-03-09 13:58:40 -08:00
Andrew Waterman
24a2278fc4
Perform all illegal-instruction detection in ID stage
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This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
2017-03-09 11:29:51 -08:00
Andrew Waterman
7668827741
Support unrolling the integer divider
2017-03-09 11:29:51 -08:00
Andrew Waterman
74d8d672bf
Improve BTB critical path at slight accuracy cost
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Make entries fully associative on lower 14 bits only, not full address.
2017-03-09 11:29:51 -08:00
Andrew Waterman
11c8857b5d
Don't re-read I$ RAMs on stall
2017-03-09 11:29:51 -08:00
Andrew Waterman
db0a02b78e
WIP on priv-1.10
2017-03-09 11:29:51 -08:00
Wesley W. Terpstra
43dea38ee9
dcache: we need the bits within the beat so select the right word ( #575 )
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We now have confirmation that it fixed the problem.
2017-03-08 00:19:09 -08:00
Andrew Waterman
603b8af2eb
Don't canonicalize 32-bit FP results in the various pipelines
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It's redundant with the new scheme, so just adds HW for no reason.
2017-03-07 20:51:32 -08:00
Andrew Waterman
f505aba1ac
Use sNaN value for flw, like other single-precision ops
2017-03-07 20:51:32 -08:00
Andrew Waterman
cc389bea90
Fix in-register representation of fdiv.s/fsqrt.s result
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We were zero-extending it, which is a double-precision zero in the recoded
format. So, when spilled and reloaded with fsd/fld, the original value
was destroyed. Instead, set the MSBs so that it represents sNaN. When
spilled, the single-precision number will be preserved as the NaN payload.
2017-03-07 20:51:32 -08:00
Henry Cook
d0ae087587
rocket: allow scratchpad address to be configurable ( #570 )
2017-03-06 21:35:45 -08:00
Henry Cook
229fb2251d
coreplex: hack to fix tile dedup ( #569 )
2017-03-06 16:36:03 -08:00
Wesley W. Terpstra
676974281a
rocket: describe dcache scratchpad as memory
2017-03-03 02:54:48 -08:00
Wesley W. Terpstra
1eeaa390c6
diplomacy: output JSON formatted version of DTS
2017-03-03 02:45:11 -08:00
Wesley W. Terpstra
0178248551
diplomacy: evaluate ResourceBindings only once
2017-03-03 02:04:17 -08:00
Wesley W. Terpstra
8e4f348dda
rocket: if no MMU, don't print it in DTS
2017-03-03 00:48:26 -08:00
Wesley W. Terpstra
7660be039c
rocketchip: add WithTimebase to set RTC frequency
2017-03-03 00:47:50 -08:00
Wesley W. Terpstra
57a329408c
PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0
2017-03-03 00:28:55 -08:00
Wesley W. Terpstra
4535de2669
rocket: use diplomatic interrupts
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This makes it possible for the PLIC to work with heterogenous cores.
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
d3c5318714
build: remove the now obsolete config string
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
93ca555c20
IntXing: support configurable sync depth
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
637bc6c3a7
coreplex: pretty print discontiguous ranges properly
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
7ff9f88ad7
rocket: connect interrupt map for Plic+Clint
2017-03-02 21:19:22 -08:00