Logo
Explore Help
Sign In
riscv/rocket-chip
Watch 1
Star 0
Fork 0
Code Releases Activity
Files
d6ab929c41d782aed81998cf0dab1a4ab7a9fdcd
rocket-chip/src/main/scala
T
History
Megan Wachs d6ab929c41 debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
..
config
Configs: use a uniform syntax without Match exceptions (#507)
2017-01-13 14:41:19 -08:00
coreplex
debug: Breaking change until FESVR is updated as well.
2017-03-27 21:19:08 -07:00
diplomacy
GenerateBootROM: use compiled DTB
2017-03-24 18:18:01 -07:00
groundtest
Fix groundtest to provide missing signals to TLB
2017-03-26 14:20:16 -07:00
jtag
Add ucb-art/chisel-jtag (#612)
2017-03-26 18:03:21 -07:00
junctions
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
regmapper
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
rocket
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
rocketchip
debug: Breaking change until FESVR is updated as well.
2017-03-27 21:19:08 -07:00
tile
Add local interrupts to core (but not yet to coreplex)
2017-03-27 16:37:09 -07:00
uncore
debug: Breaking change until FESVR is updated as well.
2017-03-27 21:19:08 -07:00
unittest
apb: put both aFlow options under regression
2017-03-16 15:36:14 -07:00
util
Util: Add ResetCatchAndSync for synchronous deassert of Async Reset (#615)
2017-03-27 03:29:07 -07:00
Powered by Gitea Version: 1.27.1 Page: 14ms Template: 4ms
Dark
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API