Wesley W. Terpstra
61a6f94196
axi4: get unit tests legal again
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
bf5cb396b9
rocketchip: relax mmio no-interleaving requirement
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
24f577c156
axi4: Deinterleaver ensures R channel ID does not change till last
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
b4188ee625
axi4: ToTL supporting pipelined MMIO
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
ca2cb033cd
rocketchip: fix uses of AXI4 Fragmenter
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e100a943ea
axi4: simplify Fragmenter by using user bits
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
7a1d107c9e
rocketchip: include an ErrorSlave by default
2017-05-01 22:53:37 -07:00
Wesley W. Terpstra
641a4d577a
tilelink2: Error device for returning errors on demand
2017-05-01 22:53:02 -07:00
Wesley W. Terpstra
a580b17ece
axi4: IdIndexer => reduce number of needed ids
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
06efc01d96
axi4: an adapter to remove user bits
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
f1217519f1
axi4: RegisterRouter; concurrent response illegal in AXI
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
5163ccd11f
axi4: RegisterRouter supports user bits
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
de6ea9b442
axi4: support user bits in SRAM
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
396ecacda4
AXI4: add an optional user bundle field
2017-05-01 22:53:01 -07:00
Andrew Waterman
d6e69066a5
Fix ITIM loads ( #716 )
...
An incorrectly-set ready signal caused bad data to be read from the RAM.
2017-05-01 17:41:25 -07:00
Andrew Waterman
dd85d7e0a0
I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle
...
@solomatnikov found the bug. It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
2017-04-28 16:44:58 -07:00
Megan Wachs
d67738204f
Interrupts: Less Pessimistic Synchronization ( #714 )
...
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.
* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC
* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.
* interrupts: use consistent async/periph/core ordering
* interrupts: Properly condition on 0 External interrupts
* interrupts: CLINT is also synchronous to periph clock
2017-04-28 14:49:24 -07:00
Andrew Waterman
7416f2a17e
Unbreak groundtest
2017-04-28 02:10:33 -07:00
Andrew Waterman
8fd5ecdff8
Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR
2017-04-27 19:50:38 -07:00
Andrew Waterman
7c70aa593e
Minor stylistic and QoR improvements to PLIC
2017-04-27 19:35:20 -07:00
Henry Cook
3d0ed80ef6
new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels
2017-04-27 18:17:31 -07:00
Henry Cook
bdb526a9f0
coreplex: DefaultCoreplex => RocketPlex
2017-04-27 18:17:09 -07:00
Andrew Waterman
99de42d34c
Swap order of ITIM WidthWidget and Fragmenter
...
e99fa057ac
accidentally reversed them
2017-04-27 15:30:02 -07:00
Andrew Waterman
8c10caeef9
Express PMP mask generation with incrementer, not adder
...
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
2017-04-27 15:16:29 -07:00
Henry Cook
e99fa057ac
cleanup scratchpad nodes
2017-04-27 14:02:05 -07:00
Andrew Waterman
b2b4725522
Fix zero-width wire issues when ITIM is disabled
2017-04-26 22:43:00 -07:00
Andrew Waterman
e23ee274f6
Size hartid field with NTiles, not XLen
2017-04-26 20:11:43 -07:00
Andrew Waterman
dc753bfa95
Fix I$ elaboration when ITIM is disabled
2017-04-26 19:35:35 -07:00
Andrew Waterman
80d826b94a
Make DTIM deduplicatable
2017-04-26 19:35:35 -07:00
Andrew Waterman
418879a47f
Add Instruction Tightly Integrated Memory
2017-04-26 19:35:35 -07:00
Andrew Waterman
ee6702e5e0
Support indexing 1-entry Seqs
...
It's a zero-width wire special case.
Closes #706 .
2017-04-26 19:35:35 -07:00
Andrew Waterman
2e23d46631
Use val instead of def in ECC calculations
...
This allows nicer-looking code to avoid generating lots of redundant nodes.
2017-04-26 19:35:35 -07:00
Megan Wachs
7ad4cc36f7
debug: Prevent writes to DATA/PROGBUF when busy
2017-04-26 11:11:21 -07:00
Henry Cook
7f5f1c7631
Merge branch 'master' into async_queue_option
2017-04-25 14:58:11 -07:00
Henry Cook
9bb0d92381
Merge branch 'master' into async_queue_option
2017-04-25 11:23:22 -07:00
Henry Cook
60d71efa36
ahb: make hreadyout fuzzing a sram parameter
2017-04-25 11:11:31 -07:00
Henry Cook
ca435c2f40
uncore: more verbose requires
2017-04-25 11:11:31 -07:00
Wesley W. Terpstra
f3ab23d068
dcache: fix stupidly wrong crossing comparison ( #703 )
2017-04-25 09:18:41 -07:00
Wesley W. Terpstra
4807ce7ced
dcache: put a flow Q to absorb back-pressure without restarting pipeline ( #701 )
...
* dcache: put a flow Q to absorb back-pressure without restarting pipeline
When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.
* dcache: provision as few stages as possible
2017-04-24 23:28:04 -07:00
Wesley W. Terpstra
9c1d126965
Allow speculative fetch to uncacheable memory if it hits in I$ ( #700 )
...
@aswaterman it's in
2017-04-24 19:12:37 -07:00
Wesley W. Terpstra
11ff4dfbb9
rocket: seip (int 9) is only present if VM is enabled ( #699 )
2017-04-24 15:58:33 -07:00
Wesley W. Terpstra
d0f3004097
tilelink2: help tools save some registers in the WidthWidget ( #691 )
2017-04-24 15:13:58 -07:00
Andrew Waterman
65928dc6a0
Don't push RAS for "auipc ra, X; jalr ra, ra, Y"
2017-04-24 02:01:15 -07:00
Andrew Waterman
36a7971975
Bypass scoreboard to reduce MMIO latency
2017-04-24 02:01:15 -07:00
Andrew Waterman
845e6f7458
Filter out duplicate test suites
...
I botched the refactoring in 5934c7b4b9
2017-04-24 02:01:15 -07:00
Andrew Waterman
f2d4cb8152
Update RAS speculatively from fetch stage
2017-04-24 02:01:15 -07:00
Andrew Waterman
3b2c15b648
Use tininess-after-rounding in FPU
2017-04-24 02:01:15 -07:00
Andrew Waterman
c36c171202
Use correct interrupt priority order
2017-04-24 02:01:15 -07:00
Andrew Waterman
bf861293d9
Add ShiftQueue; use it
2017-04-24 02:01:15 -07:00
Andrew Waterman
d24d8ff84b
Don't stall the frontend, making it easier to add more features later
2017-04-24 02:01:15 -07:00
Andrew Waterman
061a0adceb
Fetch smaller parcels from the I$
2017-04-24 02:01:15 -07:00
Ben Keller
0aa8f7d61d
Add narrowData option to AsyncQueue.
...
This option reduces the number of wires that cross the clock boundary.
This can be a useful feature if the clock boundary coincides with
a voltage boundary, in which case the number of level shifters is reduced.
However, this introduces a path that crosses from sink->source->sink domain,
so the option is disabled by default.
2017-04-21 16:31:17 -07:00
Megan Wachs
c72b15f2a0
Down with any require() statement that makes me RTFC
2017-04-21 15:44:42 -07:00
Henry Cook
54820e094d
Make more require statements in diplomacy verbose ( #693 )
...
* diplomacy: add more verbose requirements
* bump firrtl
2017-04-20 13:18:39 -07:00
Henry Cook
ef8a819763
Miscellaneous periphery improvements ( #689 )
...
* fifofixer: work around zero-width wires for single source id
* periphery: sourceshrinker takes maxInFlight parameter
2017-04-20 11:28:00 -07:00
Megan Wachs
9002e7e532
debug: Debug Module needs to handle DMI NOPs even if DTM won't send them.
2017-04-20 10:19:50 -07:00
Megan Wachs
cc7f0a5b7a
debug: whitespace cleanup
2017-04-20 10:19:50 -07:00
Megan Wachs
5934779082
debug: Clean up ValidReg assertion.
2017-04-20 10:19:50 -07:00
Megan Wachs
0c013a56c0
debug: Make DMI NOPs really NOPs.
...
This simplifies SW design and CDC issues.
2017-04-20 10:19:50 -07:00
Andrew Waterman
67404a665b
When not using a cache, LR/SC isn't legal even on cacheable memory
2017-04-20 08:47:03 -07:00
Megan Wachs
1be13d6b4c
PLIC: To avoid hazard between enable -> claim, enforce concurrency=1
2017-04-19 21:37:37 -07:00
Megan Wachs
3dfd584075
regmapper: remove the Pipe in the RegMapper Queue
...
With this pipe here, devices which declare concurrency > 0
actually accept transactions on the same cycle they complete
the previous one. This is unexpected behavior.
2017-04-19 21:37:37 -07:00
Wesley W. Terpstra
b4d17c76d1
coreplex: make rational+synchronous crossing configurable ( #688 )
2017-04-19 16:16:05 -07:00
Megan Wachs
408107447c
debug: DMI response should be busy, not zero, when there is an error. ( #685 )
2017-04-18 21:41:52 -07:00
Andrew Waterman
d82a0dc231
Mitigate D$ exception critical path, yet again
2017-04-18 00:47:58 -07:00
Andrew Waterman
c99ce7ce5d
Only report D$ exceptions on not-nacked accesses
2017-04-18 00:47:58 -07:00
Andrew Waterman
5934c7b4b9
Fix description of LR/SC test suites
2017-04-18 00:47:58 -07:00
Andrew Waterman
a956b78dd2
In TLBPermissions, merge across some region types
...
We only care whether they have side effects or not.
2017-04-18 00:47:58 -07:00
Andrew Waterman
6de6f38894
Pipeline D$ exception response into s2
2017-04-18 00:47:58 -07:00
Andrew Waterman
657f4d4e0c
Permit early grant acks to broadcast hub
2017-04-18 00:47:58 -07:00
Andrew Waterman
cc9ec1d51a
Send D$ grant acks early; accept release acks early
...
We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
2017-04-18 00:47:58 -07:00
Andrew Waterman
728569c717
Reduce access-exception generation critical path
2017-04-18 00:47:58 -07:00
Andrew Waterman
a59a3f15e4
Disable LR/SC tests for scratchpad configs
2017-04-18 00:47:58 -07:00
Andrew Waterman
c366007a0d
Tighten PMAs for LR/SC and misaligned accesses
...
- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
2017-04-18 00:47:58 -07:00
Andrew Waterman
74a7838de0
In TLBPermissions, don't merge regions of different types
2017-04-18 00:47:58 -07:00
Andrew Waterman
7871ec82c4
Guarantee probe forward progress during LR storm
2017-04-18 00:47:58 -07:00
Andrew Waterman
debcbca7de
Make PMP tolerant to PA size << VA size
2017-04-17 10:28:33 -07:00
Andrew Waterman
a454edaaf7
Treat exceptions as steps for the purposes of single-stepping
2017-04-17 10:28:33 -07:00
Megan Wachs
af6b2d8051
debug: DATA Region has to be aligned for ld/sd to correctly detect 64-bit cores.
2017-04-17 10:28:33 -07:00
Megan Wachs
b44d5f9386
debug: correctly consider .transfer bit in COMMAND
2017-04-17 10:28:33 -07:00
Megan Wachs
79477fbea6
debug: Properly consider 'transfer' bit
2017-04-17 10:28:33 -07:00
Megan Wachs
2dc4be6294
debug: remove preexec. Simplify the state machine since you can always just 'execute' once.
2017-04-17 10:28:33 -07:00
Wesley W. Terpstra
7b8af96fc2
diplomacy: use circles for nodes again
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
2f22fca615
rocket: reverse input edge for better output
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
ae8fd0c60f
graphML: don't draw unconnected LazyModules
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
fcf774f125
graphML: reverse interrupt arrows
2017-04-14 18:09:14 -07:00
Jacob Chang
d3925f0998
Add hooks to print debug information into the graphml file
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
ba8be17c9a
tilelink2: RAMModel, use CRC16 to check AMO response
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
6aeec673f2
util: add a CRC calculator
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
d794218ec3
tilelink2: RAMModel now checks atomic results
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
4f0ae1eab7
tilelink2: annotate which test generates RAMModel output
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
0b65fe9532
unittest: put AtomicAutomata under regression
2017-04-14 15:13:39 -07:00
Wesley W. Terpstra
248acbd1b4
tilelink2: add a generic TL2 atomic evaulation unit
2017-04-14 15:13:39 -07:00
Megan Wachs
fd7f4a4c0f
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
Andrew Waterman
34d45b4fb0
Fix whitespace error
2017-04-14 01:03:11 -07:00
Andrew Waterman
fdfcffb0b2
Catch bad physical address MSBs when VA size > PA size
2017-04-14 01:03:11 -07:00
Andrew Waterman
6fbbccca3e
Improve Seq indexing QoR
2017-04-14 01:03:11 -07:00
Andrew Waterman
d203c4c654
Check AMO operation legality in TLB
2017-04-14 01:03:11 -07:00
Yunsup Lee
6359ff96e5
Several ScratchpadSlavePort bug fixes ( #676 )
...
* only replicate scratch slave d-channel resp when AMO req
* dtim: port can't support put partial mask with holes
* dtim: use \!isRead instead of isAMO
* Fix ScratchpadSlavePort looking at wrong Acquire message
Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
2017-04-13 23:25:51 -07:00
Andrew Waterman
b9e042d2bf
Unconditionally write badaddr, possibly to zero
...
59d33f6b83
2017-04-12 13:35:02 -07:00