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Author SHA1 Message Date
Henry Cook
c457c9cb9f tilelink: allow insertion of TLDelayer on TLBus outward node 2017-08-07 16:43:06 -07:00
Wesley W. Terpstra
d5a135914b Revert "Disable AMBAUnitTestConfig, as it is blocking unrelated PRs" 
This reverts commit 39b7e930ca.

Now that the RAMModel can properly tolerate overlapping responses
in the face of source reuse, we can re-enable the regression test.
 2017-08-07 16:04:02 -07:00
Yunsup Lee
03002b3106 Merge pull request #930 from freechipsproject/fix-maskrom 
maskrom: retain data for d channel is not ready
 2017-08-07 16:01:38 -07:00
Wesley W. Terpstra
f8b45564d1 tilelink: RAMModel must support source reuse 
If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
 2017-08-07 16:01:15 -07:00
Yunsup Lee
558fc7f293 maskrom: retain data for d channel is not ready 2017-08-07 12:17:10 -07:00
Yunsup Lee
aff028f8f0 Merge pull request #926 from freechipsproject/bump-tools 
bump riscv-tools
 2017-08-06 23:04:55 -07:00
Andrew Waterman
3d0051e799 bump tools for test fixes 2017-08-06 22:36:25 -07:00
Andrew Waterman
7fd8bb1159 Merge pull request #928 from freechipsproject/critical-paths 
Critical paths
 2017-08-06 18:50:59 -07:00
Andrew Waterman
658e36f98b Reduce fanout on frontend io.cpu.req.valid signal 2017-08-06 17:38:51 -07:00
Andrew Waterman
7d94074b05 Remove one gate from D$ ECC check 
The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
 2017-08-06 17:36:53 -07:00
Wesley W. Terpstra
d03fdc4f30 diplomacy: seal the LazyModuleImpLike trait (#927) 
This makes sure that all the base classes call instantiate()
 2017-08-06 17:32:23 -07:00
Yunsup Lee
5030a8b15a Merge pull request #925 from freechipsproject/fix-lazy-raw-modules 
diplomacy: provide default clock/reset for LazyRawModuleImp
 2017-08-06 14:42:14 -07:00
Yunsup Lee
aa60c6944b diplomacy: provide default clock/reset for LazyRawModuleImp 2017-08-06 13:40:07 -07:00
Yunsup Lee
6389120dbd Merge pull request #923 from freechipsproject/critical-paths 
Critical paths
 2017-08-05 17:02:22 -07:00
Andrew Waterman
39b7e930ca Disable AMBAUnitTestConfig, as it is blocking unrelated PRs 2017-08-05 16:14:02 -07:00
Andrew Waterman
83875e3a0c Only flush D$ on FENCE.I if it won't always be probed on I$ miss 2017-08-05 14:22:40 -07:00
Andrew Waterman
991e16de92 Remove probe address mux from TLB response path 2017-08-05 12:57:38 -07:00
Andrew Waterman
b9b4142bb4 Get s2_nack off the critical path 
We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively).  This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
 2017-08-05 00:30:36 -07:00
Andrew Waterman
bc298bf146 Optimize ShiftQueue for late-arriving deq.ready 2017-08-04 22:06:37 -07:00
Andrew Waterman
6112adfbb0 Get L2 TLB tag/parity check off the D$ arbitration path 2017-08-04 17:01:51 -07:00
Andrew Waterman
8d97684555 Fix L2 TLB perfctr 
It was counting conflict misses but not cold misses.
 2017-08-04 17:01:31 -07:00
Andrew Waterman
df7f09b9ce Get I$ ECC check further off critical path 2017-08-04 16:59:21 -07:00
Andrew Waterman
4bfbe75d74 Avoid pipeline replays when fetch queue is full 2017-08-04 16:59:21 -07:00
Andrew Waterman
a45997d03f Separate I$ parity error from miss signal 
Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
 2017-08-04 16:59:21 -07:00
Andrew Waterman
06a831310b Shave a gate delay off I$ backpressure path 
The deleted code was a holdover from Hwacha's vector fences.
 2017-08-04 13:12:43 -07:00
Andrew Waterman
ecc2ee366c Shave a few gate delays off IBuf control logic 
It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.
 2017-08-04 13:12:43 -07:00
Andrew Waterman
82ff81e40d Merge pull request #924 from freechipsproject/dont-build-debug-verilog 
Don't build verilog twice for emulator and emulator-debug
 2017-08-04 10:16:59 -07:00
Andrew Waterman
7937db0c84 Merge pull request #919 from freechipsproject/imiss-perf-counter 
Fix I$ miss perfctr
 2017-08-04 01:04:23 -07:00
Andrew Waterman
21ac28b57a Don't build verilog twice for emulator and emulator-debug 
Since we aren't using chisel2, the output is the same either way.
 2017-08-04 01:02:33 -07:00
Megan Wachs
017ac130c1 Merge pull request #922 from freechipsproject/bigger_tl_xbar 
TLXbar: Allow more masters and slaves and issue a warning.
 2017-08-03 16:52:56 -07:00
Megan Wachs
50c85f1b62 TLXbar: Allow more masters and slaves and issue a warning. 2017-08-03 15:46:06 -07:00
Andrew Waterman
ba4eecc0f0 Use UIntToOH1 (#921) 
Closes #920
 2017-08-03 14:55:39 -07:00
Andrew Waterman
f483bab4aa Fix I$ miss perfctr 
The old version was counting prefetches, too.
 2017-08-03 00:52:12 -07:00
Andrew Waterman
1be1433f04 Merge pull request #918 from freechipsproject/icache-prefetch 
Icache prefetch
 2017-08-02 21:22:20 -07:00
Andrew Waterman
d66e8f8e80 Merge pull request #914 from freechipsproject/critical-paths 
Fix some critical paths
 2017-08-02 19:05:31 -07:00
Megan Wachs
3fc7100048 Merge pull request #917 from freechipsproject/fuzzer_order 
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
 2017-08-02 18:39:59 -07:00
Andrew Waterman
2537d0d54e Optionally prefetch next I$ line into L2$ on miss 2017-08-02 17:10:56 -07:00
Andrew Waterman
744cdb2f72 Make TLB report when it's safe to prefetch within a page 2017-08-02 17:09:38 -07:00
Megan Wachs
d9821a74ce Merge pull request #916 from freechipsproject/transfer_sizes_print 
diplomacy: Pretty Print for TransferSizes
 2017-08-02 16:56:36 -07:00
Megan Wachs
595415d207 TLFuzzer: Correct the number of ordered clients created 2017-08-02 15:48:21 -07:00
Megan Wachs
fc5c04ed4b TLFuzzer: Allow Ordered clients to be created as well by the fuzzer 2017-08-02 14:44:18 -07:00
Andrew Waterman
7d2dd3769f Optimize a hazard check critical path 2017-08-02 14:27:25 -07:00
Megan Wachs
85bdae0fa8 diplomacy: Pretty Print for TransferSizes 2017-08-02 11:40:50 -07:00
Andrew Waterman
2eb239d03f Add option to retime D$ way mux into subsequent pipeline stage 2017-08-01 23:59:20 -07:00
Andrew Waterman
9464c6db40 Mitigate(?) frontend critical path 2017-08-01 18:51:17 -07:00
Andrew Waterman
735701382f Mitigate some I$ response valid critical paths 2017-08-01 18:51:17 -07:00
Andrew Waterman
2ecea2ef60 Don't use a pipe queue on D$ TL A-channel 
This cuts an I$->D$ path.
 2017-08-01 15:17:07 -07:00
Yunsup Lee
f988b91575 Merge pull request #912 from freechipsproject/add-mask-rom 
tilelink: add mask rom
 2017-07-31 22:28:11 -07:00
Yunsup Lee
6ef8ee5d4d tilelink: add mask rom 2017-07-31 21:34:04 -07:00
Yunsup Lee
4b33249812 Merge pull request #911 from freechipsproject/fix-dcache-bug 
Fix D$ ready-valid signaling bug
 2017-07-31 19:14:16 -07:00