0aa8f7d61d
Add narrowData option to AsyncQueue.
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This option reduces the number of wires that cross the clock boundary.
This can be a useful feature if the clock boundary coincides with
a voltage boundary, in which case the number of level shifters is reduced.
However, this introduces a path that crosses from sink->source->sink domain,
so the option is disabled by default.
2017-04-21 16:31:17 -07:00
c72b15f2a0
Down with any require() statement that makes me RTFC
2017-04-21 15:44:42 -07:00
458d80cb18
For Verilator, rename +start to +dump-start to match VCS
2017-04-20 17:00:46 -07:00
2faf8ea239
Add +dump-start=N option to VCS
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Starts dumping waveform on cycle N.
Can control stop cycle with +max-cycles.
2017-04-20 17:00:46 -07:00
54820e094d
Make more require statements in diplomacy verbose ( #693 )
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* diplomacy: add more verbose requirements
* bump firrtl
2017-04-20 13:18:39 -07:00
ef8a819763
Miscellaneous periphery improvements ( #689 )
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* fifofixer: work around zero-width wires for single source id
* periphery: sourceshrinker takes maxInFlight parameter
2017-04-20 11:28:00 -07:00
9002e7e532
debug: Debug Module needs to handle DMI NOPs even if DTM won't send them.
2017-04-20 10:19:50 -07:00
cc7f0a5b7a
debug: whitespace cleanup
2017-04-20 10:19:50 -07:00
5934779082
debug: Clean up ValidReg assertion.
2017-04-20 10:19:50 -07:00
0c013a56c0
debug: Make DMI NOPs really NOPs.
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This simplifies SW design and CDC issues.
2017-04-20 10:19:50 -07:00
67404a665b
When not using a cache, LR/SC isn't legal even on cacheable memory
2017-04-20 08:47:03 -07:00
1be13d6b4c
PLIC: To avoid hazard between enable -> claim, enforce concurrency=1
2017-04-19 21:37:37 -07:00
3dfd584075
regmapper: remove the Pipe in the RegMapper Queue
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With this pipe here, devices which declare concurrency > 0
actually accept transactions on the same cycle they complete
the previous one. This is unexpected behavior.
2017-04-19 21:37:37 -07:00
b4d17c76d1
coreplex: make rational+synchronous crossing configurable ( #688 )
2017-04-19 16:16:05 -07:00
408107447c
debug: DMI response should be busy, not zero, when there is an error. ( #685 )
2017-04-18 21:41:52 -07:00
d82a0dc231
Mitigate D$ exception critical path, yet again
2017-04-18 00:47:58 -07:00
c99ce7ce5d
Only report D$ exceptions on not-nacked accesses
2017-04-18 00:47:58 -07:00
5934c7b4b9
Fix description of LR/SC test suites
2017-04-18 00:47:58 -07:00
a956b78dd2
In TLBPermissions, merge across some region types
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We only care whether they have side effects or not.
2017-04-18 00:47:58 -07:00
6de6f38894
Pipeline D$ exception response into s2
2017-04-18 00:47:58 -07:00
657f4d4e0c
Permit early grant acks to broadcast hub
2017-04-18 00:47:58 -07:00
cc9ec1d51a
Send D$ grant acks early; accept release acks early
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We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
2017-04-18 00:47:58 -07:00
728569c717
Reduce access-exception generation critical path
2017-04-18 00:47:58 -07:00
a59a3f15e4
Disable LR/SC tests for scratchpad configs
2017-04-18 00:47:58 -07:00
c366007a0d
Tighten PMAs for LR/SC and misaligned accesses
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- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
2017-04-18 00:47:58 -07:00
74a7838de0
In TLBPermissions, don't merge regions of different types
2017-04-18 00:47:58 -07:00
7871ec82c4
Guarantee probe forward progress during LR storm
2017-04-18 00:47:58 -07:00
71eaed7d60
Merge pull request #675 from ucb-bar/debug_no_preexec
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More Debug Updates to bring in line with spec
2017-04-18 03:10:27 +09:00
1ad5ef7aa2
bump chisel
2017-04-17 10:28:33 -07:00
debcbca7de
Make PMP tolerant to PA size << VA size
2017-04-17 10:28:33 -07:00
aad4f350bf
bump tools
2017-04-17 10:28:33 -07:00
a454edaaf7
Treat exceptions as steps for the purposes of single-stepping
2017-04-17 10:28:33 -07:00
9cf86fa105
debug: checkpoint pointing to riscv-tools that picks up some tweaks in the debug riscv-tests
2017-04-17 10:28:33 -07:00
9a6e7afc93
debug: bump OpenOCD to latest version of newprogram (with Examined RISC-V core message)
2017-04-17 10:28:33 -07:00
af6b2d8051
debug: DATA Region has to be aligned for ld/sd to correctly detect 64-bit cores.
2017-04-17 10:28:33 -07:00
b44d5f9386
debug: correctly consider .transfer bit in COMMAND
2017-04-17 10:28:33 -07:00
79477fbea6
debug: Properly consider 'transfer' bit
2017-04-17 10:28:33 -07:00
2dc4be6294
debug: remove preexec. Simplify the state machine since you can always just 'execute' once.
2017-04-17 10:28:33 -07:00
c5cb8b714f
debug: Bump version and location of OpenOCD to pick up fix for off-by-1 in hartsel
2017-04-17 10:28:33 -07:00
db5d0737f0
Merge pull request #682 from ucb-bar/jchang
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Add hooks to print debug information into the graphml file
2017-04-14 19:35:17 -07:00
7b8af96fc2
diplomacy: use circles for nodes again
2017-04-14 18:09:14 -07:00
2f22fca615
rocket: reverse input edge for better output
2017-04-14 18:09:14 -07:00
ae8fd0c60f
graphML: don't draw unconnected LazyModules
2017-04-14 18:09:14 -07:00
fcf774f125
graphML: reverse interrupt arrows
2017-04-14 18:09:14 -07:00
d3925f0998
Add hooks to print debug information into the graphml file
2017-04-14 18:09:14 -07:00
153178ac4f
Merge pull request #678 from ucb-bar/rammodel-atomics
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RAMModel atomics
2017-04-14 18:08:33 -07:00
ba8be17c9a
tilelink2: RAMModel, use CRC16 to check AMO response
2017-04-14 15:13:40 -07:00
6aeec673f2
util: add a CRC calculator
2017-04-14 15:13:40 -07:00
d794218ec3
tilelink2: RAMModel now checks atomic results
2017-04-14 15:13:40 -07:00
4f0ae1eab7
tilelink2: annotate which test generates RAMModel output
2017-04-14 15:13:40 -07:00
Ben Keller
Megan Wachs
Andrew Waterman
Henry Cook
Wesley W. Terpstra
Yunsup Lee
Jacob Chang