6d6aa3eb13
tilelink2: Isolation must also connect reset_n
2016-10-10 13:13:31 -07:00
cb7b16f1a9
util: exchange resets between AsyncQueue source and sink
2016-10-10 13:13:31 -07:00
8c7d469a95
Revert "async_queue: Give names to all the registers which show up in the queue ( #390 )"
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This reverts commit a84a961a39
2016-10-10 13:13:31 -07:00
b6bc6b7a4d
Merge pull request #382 from ucb-bar/axi4
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axi4: diplomacy capable AXI4 with TL2 bridge
2016-10-10 13:11:12 -07:00
adf5f1807b
tilelink2: ToAXI4 bridge added
2016-10-10 11:21:50 -07:00
e856cbe3a6
axi4: SRAM for testing
2016-10-10 11:21:50 -07:00
abb02aa6f4
axi4: add a RegisterRouter for generic devices
2016-10-10 11:21:50 -07:00
2f7081aeaf
tilelink2: make mask generation reusable
2016-10-10 11:21:50 -07:00
b29d34038e
axi4: diplomacy capable AXI4
2016-10-10 11:21:50 -07:00
dcb9383568
PositionalMultiQueue: work around vcs Lint report
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Lint-[PCTIO-L] Ports coerced to inout
rocket-chip/vsim/generated-src/unittest.UncoreUnitTestConfig.v, 127524
"io_deq_0_valid"
Port "io_deq_0_valid" declared as output in module "PositionalMultiQueue_16"
may need to be inout. Coercing to inout.
2016-10-10 11:21:49 -07:00
5d905a5310
PositionalMultiQueue: shared storage FIFO 1-push n-pop
2016-10-10 11:21:49 -07:00
0af2a5ba02
bump tools
2016-10-09 22:15:55 -07:00
3a1d8fe482
debug: use a different form of the crossing which doesn't create an AsyncScope ( #394 )
2016-10-09 20:33:18 -07:00
b5d4b72313
register_crossing: Remove the need for AsyncScope by specifying the master clock and reset. ( #393 )
2016-10-09 15:51:23 -07:00
1e69a2dc1c
[tilelink2] allow TL monitors to be globally enabled or disabled ( #392 )
2016-10-09 12:34:10 -07:00
53360f4c2c
Disable U-mode by default unless S-mode is present
2016-10-08 21:29:40 -07:00
7f429e8799
Simplify AsyncResetReg
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No need for AsyncSetReg, as AsyncResetReg can be used exclusively with
inverted inputs.
2016-10-08 21:29:40 -07:00
a84a961a39
async_queue: Give names to all the registers which show up in the queue ( #390 )
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This is to aid debugging but even more so for backend constraint writers, who generally
need predictable names for registers to set false paths, etc.
2016-10-08 17:50:50 -07:00
4fd03ffdf1
Fix PopCountAtLeast, un-breaking BTB
2016-10-07 21:20:40 -07:00
5392219d86
bump riscv-tools
2016-10-07 15:50:43 -07:00
4c49fef242
Merge pull request #388 from ucb-bar/cp-safer-crossings
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tilelink2: split isolation gates by direction
2016-10-07 13:45:23 -07:00
e5ac0f717f
tilelink2: split isolation gates by direction
2016-10-07 12:03:43 -07:00
ad618fd55d
plic: Fix bit extraction
2016-10-06 18:05:03 -07:00
b1c777c7a2
Fix PLIC enable bit access for #ints >= tlDataBits
2016-10-06 16:21:14 -07:00
c22438b822
Fix an overly strict D$ assertion
2016-10-06 15:52:46 -07:00
fe641c14a1
tilelink2: Add support for different noise generator in fuzzer ( #386 )
2016-10-06 13:20:13 -07:00
5980dc160f
Don't allow multiple entries for same PC in BTB
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Necessary for RVC forward-progress guarantee.
2016-10-06 11:30:45 -07:00
9b8e8a8b9e
Add sbt-unidoc plugin; bump sbt-buildinfo version. ( #385 )
2016-10-06 10:48:11 -07:00
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
4f6eb38eeb
Enable Verilator parallel builds
2016-10-04 22:29:39 -07:00
6472d4c245
Print Verilator random seed when +verbose is passed
2016-10-04 22:29:39 -07:00
67593fdf2d
Explicitly zap some S-mode CSRs when not using S-mode
2016-10-04 22:29:39 -07:00
968851f7e3
Default to configurable priorities
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up-to-7 levels is kind of arbitrary, but I'm unwilling to introduce
a new Parameter at the moment.
2016-10-04 22:29:39 -07:00
e952f8f222
asyncqueue: Fix typo in the Async Queue ( #381 )
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* asyncqueue: Fix typo in the Async Queue that would cause the sync depth to be one less than expected.
* asyncqueue: Typo in the typo fix
2016-10-04 21:02:06 -07:00
064c9ebdc6
Don't report I$ fetch faults on TLB misses!
2016-10-04 14:37:25 -07:00
516481b68b
Improve back-to-back integer multiplication performance
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More exact hazard checking in the decode stage avoids a pipeline flush.
2016-10-04 14:37:25 -07:00
7b69f1f261
Don't enter D$ flush state machine if grant outstanding
2016-10-04 14:37:25 -07:00
28beb33943
Make any intervening load/store/fence fail an LR/SC sequence
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This catches LR/SC misuses more quickly.
2016-10-04 14:37:25 -07:00
23c8b06d4a
use $urandom as seed for $random
2016-10-03 17:56:30 -07:00
62954d543e
correctly initialize the active flag
2016-10-03 17:56:30 -07:00
6ec2e7c5bd
tilelink2: Legacy should preserve the access size ( #378 )
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* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
2016-10-03 17:25:31 -07:00
72e8c6f589
Merge pull request #379 from ucb-bar/axi-prefactor
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Axi prefactor
2016-10-03 16:49:37 -07:00
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
c85e42a303
tilelink2: Nodes should accept full PortParameters
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We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
2016-10-03 16:09:49 -07:00
f2ca2178bf
graphML: CTO's like colour
2016-10-03 15:05:45 -07:00
fe0875b084
LazyModule: output final verilog Module name
2016-10-03 15:05:45 -07:00
0a4ef66894
BaseTop: record top module; more general than GraphML
2016-10-03 15:05:45 -07:00
5ff3d3d61c
correctly initialize with seed
2016-10-02 17:31:32 -07:00
52c1a053ff
tilelink2 RegisterRouter: test fully Decoupled behaviour
2016-10-02 02:24:02 -07:00
422e6357a4
tilelink2 RegisterCrossing: Queues go from RV to Irrevocable
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AsyncQueue is still a Queue.
2016-10-02 02:24:02 -07:00
