Henry Cook
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d46e59a16d
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Abstract base nbcache class
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2012-02-16 12:34:51 -08:00 |
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Henry Cook
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124efe5281
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Replace nbcache manipulation of meta state bits with abstracted functions
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2012-02-16 10:43:40 -08:00 |
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Henry Cook
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619929eba1
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Added coherence tile function defs, with traits and constants
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2012-02-16 00:16:45 -08:00 |
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Andrew Waterman
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1b5e39e7fc
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fix bug in BTB
a BTB update followed by a taken branch could cause incorrect control flow.
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2012-02-15 21:36:08 -08:00 |
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Andrew Waterman
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fc5ba769da
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disable vector unit by default
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2012-02-15 18:58:41 -08:00 |
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Andrew Waterman
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8b3b3abd3d
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fix external memory request nack logic
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2012-02-15 18:57:40 -08:00 |
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Andrew Waterman
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fe2c1d1321
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add vec->ctrl fences
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2012-02-15 18:31:19 -08:00 |
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Yunsup Lee
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82cd3625c2
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add in vackq interface
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2012-02-15 17:53:24 -08:00 |
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Andrew Waterman
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c13524ad3a
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fix vcmdq full replay logic
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2012-02-15 17:49:12 -08:00 |
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Yunsup Lee
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258d050e1b
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add stall logic for vector command queues
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2012-02-15 14:48:41 -08:00 |
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Yunsup Lee
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32bdf5098a
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refactor vector control logic & datapath in the rocket core
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2012-02-15 13:30:22 -08:00 |
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Yunsup Lee
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7c11c1406c
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vector-vector add working!
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2012-02-15 02:28:07 -08:00 |
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Yunsup Lee
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6bdf9dc513
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hwacha integration: now it compiles correctly!
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2012-02-14 23:34:57 -08:00 |
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Yunsup Lee
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a51c7cc927
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new build system with updated chisel, hwacha
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2012-02-14 19:43:59 -08:00 |
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Andrew Waterman
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0ec7767c13
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declaring success on FPU for now
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2012-02-14 19:11:57 -08:00 |
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Andrew Waterman
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297223a13c
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squash subsequent external mem request after nack
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2012-02-14 15:12:16 -08:00 |
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Andrew Waterman
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38c67e5a9e
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add fmin.[s|d] and fmax.[s|d]
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2012-02-14 06:37:18 -08:00 |
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Andrew Waterman
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ee9fc10668
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add fcvt.s.d, fcvt.d.s
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2012-02-14 06:03:43 -08:00 |
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Andrew Waterman
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ce202c73d1
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add fsgnj[n|x].[s|d]
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2012-02-14 04:24:35 -08:00 |
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Andrew Waterman
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1d604bcd49
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remove top-level Makefile
new, simpler build instructions are in the README.
note that for "make run-asm-tests-debug" you need to update your fesvr.
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2012-02-14 02:53:43 -08:00 |
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Andrew Waterman
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15dc2d8c40
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add fp writeback arbitration logic
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2012-02-14 00:32:25 -08:00 |
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Henry Cook
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0671a99712
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NBcache works with associativities other than powers of 2
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2012-02-13 21:44:32 -08:00 |
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Henry Cook
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6d36168183
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Fixed two associative nbcache bugs, one in amo replays and one in the flush unit
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2012-02-13 21:44:32 -08:00 |
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Andrew Waterman
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0366465cb1
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parameterize the scoreboards
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2012-02-13 18:12:23 -08:00 |
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Andrew Waterman
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6c2d8a37ae
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remove a partial update that makes chisel barf
chisel regards it as a combinational loop, even though it isn't.
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2012-02-13 16:45:29 -08:00 |
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Andrew Waterman
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c78c738f60
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minor cleanups
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2012-02-13 03:13:49 -08:00 |
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Andrew Waterman
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b5a19a54a3
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add fcvt.[s|d].[w|l][u]
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2012-02-13 02:01:26 -08:00 |
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Andrew Waterman
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a4a9d2312c
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add fcvt.[w|l][u].[s|d], f[eq|lt|le].[s|d]
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2012-02-13 01:30:01 -08:00 |
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Andrew Waterman
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069037ff3a
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add FP recoding
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2012-02-12 23:31:50 -08:00 |
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Andrew Waterman
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25ecfb9bbc
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clean up caches
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
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2012-02-12 20:32:06 -08:00 |
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Andrew Waterman
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08b6517a23
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add FP ops mftx, mxtf, mtfsr, mffsr
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2012-02-12 20:12:53 -08:00 |
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Andrew Waterman
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9bb1558a34
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WIP on FPU
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2012-02-12 04:36:01 -08:00 |
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Andrew Waterman
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50a283d311
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move store data generation into EX stage
doing so removes it from the critical path of FP store unrecoding.
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2012-02-12 01:35:55 -08:00 |
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Andrew Waterman
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725190d0ee
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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Andrew Waterman
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f8b937d590
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fix 32-bit divider bug
thanks, torture!
also, tidied up the code a bit.
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2012-02-09 03:47:59 -08:00 |
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Andrew Waterman
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03ee49f424
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fix 32-bit AMOs to upper halves of 64-bit words
thanks, torture!
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2012-02-09 03:31:47 -08:00 |
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Yunsup Lee
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f47d888feb
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vvcfgivl and vsetvl works
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2012-02-09 02:35:21 -08:00 |
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Andrew Waterman
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92493ad153
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fix mul/div kill bug
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
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2012-02-09 02:26:03 -08:00 |
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Andrew Waterman
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128ec567ed
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make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
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2012-02-09 01:34:00 -08:00 |
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Yunsup Lee
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fcc8081c4d
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hook up the vector command queue
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2012-02-09 01:28:16 -08:00 |
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Andrew Waterman
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8b6b0f5367
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add external memory request interface for vec unit
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2012-02-08 22:30:45 -08:00 |
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Yunsup Lee
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9285a52f25
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initial vu integration
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2012-02-08 21:43:45 -08:00 |
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Andrew Waterman
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10b5a0006c
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fix mul/div to rd=0
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2012-02-08 20:11:57 -08:00 |
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Andrew Waterman
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a1855b12c2
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clean up queues
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2012-02-08 17:55:05 -08:00 |
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Andrew Waterman
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990e3a1b34
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fix fpu port direction bug
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2012-02-08 15:19:26 -08:00 |
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Andrew Waterman
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b3f6f9a5fd
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fix BTB misprediction check for negative addresses
also index BTB with PC, not PC+4
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2012-02-08 15:05:28 -08:00 |
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Andrew Waterman
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e9da2cf66a
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improve id/ex datapath
move operand selection into decode stage; simplify bypassing
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2012-02-08 06:47:26 -08:00 |
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Andrew Waterman
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d471a8b2da
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arbitrate for LLFU writebacks in MEM stage
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2012-02-08 04:21:05 -08:00 |
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Andrew Waterman
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ebed56500e
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fix mul/wb hazard checks
I erroneously assumed that those instructions set id_wen.
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2012-02-08 01:56:11 -08:00 |
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Andrew Waterman
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5403d069e9
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add fp loads/stores
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2012-02-07 23:54:25 -08:00 |
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