1
0
Commit Graph

68 Commits

Author SHA1 Message Date
ac205ca10a bootrom: move to 0x10000 for more space (DTB on multicore is big) 2017-03-24 18:18:01 -07:00
34f8ce653a bootrom: follow SBI (a0=hartid, a1=dtb) 2017-03-24 18:18:01 -07:00
9a2f0d01a1 GenerateBootROM: use compiled DTB 2017-03-24 18:18:01 -07:00
57a329408c PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0 2017-03-03 00:28:55 -08:00
d3c5318714 build: remove the now obsolete config string 2017-03-02 21:19:23 -08:00
38489ad9b0 tilelink2: bring IntNode parameters up to the current standard 2017-03-02 21:19:22 -08:00
cfd367248f rocketchip: add blind ports to DTS 2017-03-02 21:19:22 -08:00
62f5727bc6 periphery: peripheryBusBytes and socBusBytes 2017-02-27 19:19:41 -08:00
a281ad8ad2 rocketchip: rename some periphery ports 2017-02-23 18:28:04 -08:00
6c3011d513 periphery: make external interrupts a UInt rather than a Vec[Bool] 2017-02-23 18:27:44 -08:00
e8c8d2af71 Heterogeneous Tiles (#550)
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
2017-02-09 13:59:09 -08:00
a3e56cfa5e rocketchip: add Zero device to the memory subsystem 2017-02-03 17:19:24 -08:00
b240505a15 rocketchip: move memory channel Xbar from coreplex to rocketchip
We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.
2017-02-03 17:19:21 -08:00
24ee7f45f5 rocketchip: pass variable l1tol2 connections into coreplex 2017-01-29 11:18:36 -08:00
3a5e5a65f8 coreplex: support multiple memory channels via diplomatic trickery 2017-01-19 19:07:14 -08:00
e7b35b4bb6 diplomacy: support multiple ports behind a BlindNode 2017-01-19 19:07:14 -08:00
9a6634cd40 Add TLBuffers on the L1 backends and blind exit points (#513)
* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
2017-01-17 11:57:23 -08:00
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
a670f63c81 periphery: a handy trait to turn-off ExtMem 2016-11-23 20:44:45 -08:00
e87f54d4f7 rocketchip: traits for adding external TL2 ports 2016-11-23 20:44:42 -08:00
1e7d597fd3 rocketchip: don't waste too many sources on the AXI master port 2016-11-22 21:48:41 -08:00
13190a5de0 rocketchip: re-add AXI4 interface 2016-11-22 17:27:58 -08:00
a140b07009 rocketchip: cut coreplex from rocketchip 2016-11-22 17:27:58 -08:00
3d644b943c coreplex: configString is a property of the RISCVPlatform 2016-11-21 21:13:26 -08:00
37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
179c93db42 tilelink2 broadcast: make it controlled via Config 2016-11-17 17:26:49 -08:00
f4ca5ea1f3 rocketchip: match simulated memory width to ExtMem.beatBytes 2016-11-17 15:40:47 -08:00
12d0d8bea2 rocketchip: remove obsolete bus configuration 2016-11-17 14:30:15 -08:00
c82b371354 rocketchip: remove obsolete TL1 config 2016-11-17 14:24:45 -08:00
dfc3a0dafb tilelink2: do not depend on obsolete TL1 configuration 2016-11-17 14:07:53 -08:00
84f249bd03 [rocketchip] BigInt cast 2016-11-16 18:11:06 -08:00
408e78e35e rocketchip Periphery: ExtMem and ExtBus Configs 2016-11-16 16:50:30 -08:00
10e459fedb rocket: change connection between rocketchip and coreplex
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
385b5d5698 axi4: default should be GET_EFFECTS 2016-11-14 15:19:39 -08:00
32fd11935c rocketchip: use TL2 and AXI4 for memory subsytem 2016-11-04 13:36:47 -07:00
5bca13ebdb rocketchip: use self-type constraints 2016-10-31 11:42:47 -07:00
ba529c3716 rocketchip: use TileLink2 interrupts 2016-10-31 11:42:47 -07:00
a73aa351ca rocketchip: fix all clock crossings 2016-10-31 11:42:13 -07:00
825c253a72 rocketchip: move TL2 and cake pattern into Coreplex 2016-10-31 11:42:13 -07:00
f8a0829134 rocketchip: remove clint; it moves into coreplex 2016-10-31 11:42:13 -07:00
3df797fcab rocketchip: replace TL1 MMIO with an example of TL2 MMIO 2016-10-31 11:41:18 -07:00
67ab27f5a5 diplomacy: guess the LazyModule name from the containing class 2016-10-25 15:58:09 -07:00
7dc97674d6 rocketchip: include an socBus between l1tol2 and periphery (#415)
Sometimes we have high performance devices that go inbetween.
2016-10-24 23:56:09 -07:00
f05298d9bc tilelink2: move general-purpose code out of tilelink2 package 2016-10-03 16:22:28 -07:00
9910c69c67 Move a bunch more things into util package
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
c45cc76cef Get rid of remaining MemIO code
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
2016-09-27 16:28:17 -07:00
71a9c78e4b add WidthAdapter from AXI slave to Coreplex TL slave 2016-09-27 12:48:01 -07:00
7d6fb950b6 Give TileLink IDs more sensible names
* Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams
2016-09-27 12:48:01 -07:00
8a55521b01 move memory width adapter from coreplex to periphery 2016-09-27 12:48:01 -07:00
e36441a046 use correct parameters object for MMIO width adapter 2016-09-27 12:48:01 -07:00