riscv/rocket-chip
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1831 Commits

Author SHA1 Message Date
Palmer Dabbelt
cc1e2af336 Merge pull request #934 from freechipsproject/critical-paths 
Revert "Remove one gate from D$ ECC check"
 2017-08-07 19:41:08 -07:00
Henry Cook
c8f8806df0 Merge pull request #932 from freechipsproject/tl-bus-delayer 
tilelink: allow insertion of TLDelayer on TLBus outward node
 2017-08-07 19:01:39 -07:00
Henry Cook
c4092dd0cc tilelink: improve entropy of bus delayer 2017-08-07 17:36:07 -07:00
Andrew Waterman
402907990c Revert "Remove one gate from D$ ECC check" 
This reverts commit 7d94074b05, which
works fine with optimistic behavioral RAMs but not real ones.
 2017-08-07 17:33:20 -07:00
Henry Cook
2910d6fa2a tilelink: make bus xbar protected so it can be suggestNamed 2017-08-07 17:30:24 -07:00
Palmer Dabbelt
fc0d5fcf98 Print out the compressed instruction when executing one 2017-08-07 17:21:53 -07:00
Wesley W. Terpstra
e27072e063 Merge pull request #931 from freechipsproject/fix-ram-model-source-reuse 
Fix ram model source reuse
 2017-08-07 16:56:13 -07:00
Henry Cook
c457c9cb9f tilelink: allow insertion of TLDelayer on TLBus outward node 2017-08-07 16:43:06 -07:00
Wesley W. Terpstra
f8b45564d1 tilelink: RAMModel must support source reuse 
If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
 2017-08-07 16:01:15 -07:00
Yunsup Lee
558fc7f293 maskrom: retain data for d channel is not ready 2017-08-07 12:17:10 -07:00
Andrew Waterman
7fd8bb1159 Merge pull request #928 from freechipsproject/critical-paths 
Critical paths
 2017-08-06 18:50:59 -07:00
Andrew Waterman
658e36f98b Reduce fanout on frontend io.cpu.req.valid signal 2017-08-06 17:38:51 -07:00
Andrew Waterman
7d94074b05 Remove one gate from D$ ECC check 
The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
 2017-08-06 17:36:53 -07:00
Wesley W. Terpstra
d03fdc4f30 diplomacy: seal the LazyModuleImpLike trait (#927) 
This makes sure that all the base classes call instantiate()
 2017-08-06 17:32:23 -07:00
Yunsup Lee
aa60c6944b diplomacy: provide default clock/reset for LazyRawModuleImp 2017-08-06 13:40:07 -07:00
Andrew Waterman
83875e3a0c Only flush D$ on FENCE.I if it won't always be probed on I$ miss 2017-08-05 14:22:40 -07:00
Andrew Waterman
991e16de92 Remove probe address mux from TLB response path 2017-08-05 12:57:38 -07:00
Andrew Waterman
b9b4142bb4 Get s2_nack off the critical path 
We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively).  This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
 2017-08-05 00:30:36 -07:00
Andrew Waterman
bc298bf146 Optimize ShiftQueue for late-arriving deq.ready 2017-08-04 22:06:37 -07:00
Andrew Waterman
6112adfbb0 Get L2 TLB tag/parity check off the D$ arbitration path 2017-08-04 17:01:51 -07:00
Andrew Waterman
8d97684555 Fix L2 TLB perfctr 
It was counting conflict misses but not cold misses.
 2017-08-04 17:01:31 -07:00
Andrew Waterman
df7f09b9ce Get I$ ECC check further off critical path 2017-08-04 16:59:21 -07:00
Andrew Waterman
4bfbe75d74 Avoid pipeline replays when fetch queue is full 2017-08-04 16:59:21 -07:00
Andrew Waterman
a45997d03f Separate I$ parity error from miss signal 
Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
 2017-08-04 16:59:21 -07:00
Andrew Waterman
06a831310b Shave a gate delay off I$ backpressure path 
The deleted code was a holdover from Hwacha's vector fences.
 2017-08-04 13:12:43 -07:00
Andrew Waterman
ecc2ee366c Shave a few gate delays off IBuf control logic 
It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.
 2017-08-04 13:12:43 -07:00
Andrew Waterman
7937db0c84 Merge pull request #919 from freechipsproject/imiss-perf-counter 
Fix I$ miss perfctr
 2017-08-04 01:04:23 -07:00
Megan Wachs
017ac130c1 Merge pull request #922 from freechipsproject/bigger_tl_xbar 
TLXbar: Allow more masters and slaves and issue a warning.
 2017-08-03 16:52:56 -07:00
Megan Wachs
50c85f1b62 TLXbar: Allow more masters and slaves and issue a warning. 2017-08-03 15:46:06 -07:00
Andrew Waterman
ba4eecc0f0 Use UIntToOH1 (#921) 
Closes #920
 2017-08-03 14:55:39 -07:00
Andrew Waterman
f483bab4aa Fix I$ miss perfctr 
The old version was counting prefetches, too.
 2017-08-03 00:52:12 -07:00
Andrew Waterman
1be1433f04 Merge pull request #918 from freechipsproject/icache-prefetch 
Icache prefetch
 2017-08-02 21:22:20 -07:00
Andrew Waterman
d66e8f8e80 Merge pull request #914 from freechipsproject/critical-paths 
Fix some critical paths
 2017-08-02 19:05:31 -07:00
Megan Wachs
3fc7100048 Merge pull request #917 from freechipsproject/fuzzer_order 
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
 2017-08-02 18:39:59 -07:00
Andrew Waterman
2537d0d54e Optionally prefetch next I$ line into L2$ on miss 2017-08-02 17:10:56 -07:00
Andrew Waterman
744cdb2f72 Make TLB report when it's safe to prefetch within a page 2017-08-02 17:09:38 -07:00
Megan Wachs
595415d207 TLFuzzer: Correct the number of ordered clients created 2017-08-02 15:48:21 -07:00
Megan Wachs
fc5c04ed4b TLFuzzer: Allow Ordered clients to be created as well by the fuzzer 2017-08-02 14:44:18 -07:00
Andrew Waterman
7d2dd3769f Optimize a hazard check critical path 2017-08-02 14:27:25 -07:00
Megan Wachs
85bdae0fa8 diplomacy: Pretty Print for TransferSizes 2017-08-02 11:40:50 -07:00
Andrew Waterman
2eb239d03f Add option to retime D$ way mux into subsequent pipeline stage 2017-08-01 23:59:20 -07:00
Andrew Waterman
9464c6db40 Mitigate(?) frontend critical path 2017-08-01 18:51:17 -07:00
Andrew Waterman
735701382f Mitigate some I$ response valid critical paths 2017-08-01 18:51:17 -07:00
Andrew Waterman
2ecea2ef60 Don't use a pipe queue on D$ TL A-channel 
This cuts an I$->D$ path.
 2017-08-01 15:17:07 -07:00
Yunsup Lee
6ef8ee5d4d tilelink: add mask rom 2017-07-31 21:34:04 -07:00
Yunsup Lee
4b33249812 Merge pull request #911 from freechipsproject/fix-dcache-bug 
Fix D$ ready-valid signaling bug
 2017-07-31 19:14:16 -07:00
Wesley W. Terpstra
42ff74bd34 Merge pull request #910 from freechipsproject/tilelink-map 
Tilelink map
 2017-07-31 18:33:09 -07:00
Andrew Waterman
e140893a01 Use 1-entry queue on processor-side E-channel 
The cache can't sink a grant every cycle, so extra E buffering doesn't help.
 2017-07-31 18:06:54 -07:00
Andrew Waterman
5681693ccc Fix a D$ ready-valid signaling regression 
I broke this in 66d06460fa.
 2017-07-31 18:05:14 -07:00
Wesley W. Terpstra
d7fd9d2b82 tilelink: Filter, add another case 2017-07-31 16:51:26 -07:00
Yunsup Lee
71a250b071 Merge pull request #909 from freechipsproject/tile-buffer 
add optional tile boundary buffers
 2017-07-31 16:46:22 -07:00
Wesley W. Terpstra
b126105230 tilelink: add TLMap to make it possible to move slaves 2017-07-31 16:39:00 -07:00
Wesley W. Terpstra
13d3ffbcaa tilelink: Filter now support arbitrary filter functions 2017-07-31 16:38:38 -07:00
Yunsup Lee
7adfd5c431 Merge pull request #906 from freechipsproject/critical-paths 
Mitigate I$->D$->I$ critical path
 2017-07-31 16:14:11 -07:00
Yunsup Lee
f473e6bad0 tile: add optional boundary buffers 2017-07-31 15:57:22 -07:00
Yunsup Lee
cb3529bbc3 util: tweak rational crossings to avoid mux in source 2017-07-31 15:10:15 -07:00
Henry Cook
11332c1226 dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative 2017-07-31 14:03:30 -07:00
Andrew Waterman
d811692c3b Mitigate I$->D$->I$ critical path 
This seemingly irrelevant change shaves several gate delays off the I$
tl.a.valid path.
 2017-07-31 01:43:04 -07:00
Andrew Waterman
ac4339a8e7 Pass D$ backpressure to D-channel, rather than asserting 2017-07-29 11:48:36 -07:00
Andrew Waterman
edcd2c696c Avoid needless stall on E-channel back pressure 2017-07-29 11:47:58 -07:00
Wesley W. Terpstra
8e2e931770 Merge pull request #903 from freechipsproject/monitor-probes 
tilelink: use the Monitor to enforce Probe sourcing
 2017-07-29 01:12:08 -07:00
Wesley W. Terpstra
56e28026a6 TLError: does not need to be fast; cut the loop 
The SystemBus already has a flow buffer on outputs.
 2017-07-29 00:22:21 -07:00
Wesley W. Terpstra
540256e24a systembus: all slaves should have an output buffer 2017-07-29 00:13:33 -07:00
Wesley W. Terpstra
eadf4e9fcc Revert "tile: add option for tile boundary buffers" 
This reverts commit b64b87ad07.

The crossings already have buffering in those places where it was
appropriate. Adding more does not help flow through paths.
 2017-07-29 00:03:24 -07:00
Wesley W. Terpstra
68064ba260 systembus: don't double down on buffers 
The order should be:
  master => buffer|xing => fifofixer => splitter => xbar
 2017-07-29 00:02:12 -07:00
Yunsup Lee
140086e2c5 Merge pull request #902 from freechipsproject/perf-improvements 
Perf improvements
 2017-07-28 20:12:10 -07:00
Wesley W. Terpstra
a0db929003 tilelink: use the Monitor to enforce Probe sourcing 2017-07-28 18:08:00 -07:00
Megan Wachs
573890e102 Merge pull request #900 from freechipsproject/more_verbose_requires 
diplomacy: More verbose require
 2017-07-28 13:23:33 -07:00
Andrew Waterman
fdb8935712 Improve fidelity of two perf counters 2017-07-28 13:14:04 -07:00
Andrew Waterman
4c82f6b77e Don't refill BTB on not-taken branches 2017-07-28 13:13:52 -07:00
Andrew Waterman
2e8b02e780 Merge D$ store hits when ECC is enabled 
This avoids pipeline flushes due to subword WAW hazards, as with
consecutive byte stores.
 2017-07-28 12:56:36 -07:00
Andrew Waterman
838864870e Bypass TLB refill signal to halve L2 TLB hit time 
The 4-cycle hit time is 1 cycle too long to avoid a second
pipeline replay, so it was effectively 9 cycles instead of 4.
 2017-07-28 12:56:36 -07:00
Andrew Waterman
ae1f7a95f6 Don't nack misses when there's a pending store 
That effectively increased the miss latency by 5 cycles when there was
a store hit followed by a load miss.  Since pending stores are drained
when releaseInFlight, the check I removed was redundant.
 2017-07-28 12:56:36 -07:00
Henry Cook
7eeb9dfd88 Merge pull request #899 from freechipsproject/wrapper-dedup 
Stabilize tile wrappers for downstream tools
 2017-07-28 10:52:59 -07:00
Megan Wachs
f61fe2be1e diplomacy: More verbose require 2017-07-28 10:05:45 -07:00
Wesley W. Terpstra
5f81c2243f tilelink: add BusBypass, useful to turn devices off 2017-07-27 20:16:30 -07:00
Wesley W. Terpstra
9a36755b6a tilelink: CacheCork uses constructor helpers 2017-07-27 18:38:15 -07:00
Wesley W. Terpstra
45189c3e30 tilelink: CacheCork now supports errors and BtoT upgrade 
- Acquire.BtoT succeeds with toT instantly
- AccessAckData.error causes Grant.toN.error
 2017-07-27 18:38:13 -07:00
Wesley W. Terpstra
2e4f1611ed tilelink: Error device supports Acquire 
We need this if we want to divert traffic to it from a TL-C slave.
 2017-07-27 18:32:58 -07:00
Henry Cook
b64b87ad07 tile: add option for tile boundary buffers 2017-07-27 17:30:51 -07:00
Henry Cook
289ef30dbc coreplex: change AsynchronousCrossing.sync default to 3 2017-07-27 15:44:51 -07:00
Henry Cook
266ed56e8d tile: turn off more slave port monitors 2017-07-27 15:28:53 -07:00
Henry Cook
9a483af6e8 coreplex: naming of tile wrappers 2017-07-27 15:16:48 -07:00
Henry Cook
33852ef965 coreplex: remove superfluous sink and source from wrapper 2017-07-27 14:23:03 -07:00
Wesley W. Terpstra
651da73d89 tilelink: it is now legal to support Acquire for UNCACHED regions 
These cases exist:
  GET_EFFECTS, PUT_EFFECTS, UNCACHEABLE && !supportsAcquire: MMIO
  UNCACHED && !supportsAcquire: speculation ok and may be cached
  UNCACHED && supportsAcquire: LLC/CacheCork applied (slave never probes)
  CACHED, TRACKED && supportsAcquire: slave might probe
 2017-07-27 11:11:22 -07:00
Wesley W. Terpstra
0ab5cb67b3 tilelink: fix RAMModel handling of AMOs on early source reuse (#897) 2017-07-27 11:07:13 -07:00
Wesley W. Terpstra
9804bdc34e tilelink: remove obsolete addr_lo signal (#895) 
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
 2017-07-26 16:01:21 -07:00
Wesley W. Terpstra
d096d5d1c4 tilelink: fix AtomicAutomata bug wrt early source reuse 
The new fuzzer already found it's first victim.
 2017-07-26 12:52:29 -07:00
Wesley W. Terpstra
6550ae2e31 tilelink: increase Fuzzer source reuse aggression 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
1efdca106c tilelink: RAMModel support early reuse of source 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
138276fd87 tilelink: SourceShrinker should work also for 0 latency 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
b2edca2a6b tilelink: cut WidthWidget from dependency on addr_lo 2017-07-26 10:31:09 -07:00
Wesley W. Terpstra
ede87c1f73 tilelink: rewrite WidthWidget beat splitter 
- split the data based on the address, not the mask
  (the first version of TileLink did not have low address bits)
- the dependency on addr_lo is now exposed and easy to replace
 2017-07-26 10:24:16 -07:00
Wesley W. Terpstra
0f5065fbf3 tilelink: WidthWidget rewrite beat merging 
- errors are properly OR reduced
- registers latched only as needed (was previously a shift register)
- combines beats without inspecting address (removes addr_lo dependency)
 2017-07-26 10:24:12 -07:00
Wesley W. Terpstra
f0ffb7e31e tilelink: initialize toggle in Fragmenter (#894) 
No strictly necessary, because the initial value does not matter, but good hygiene since it drives a cycle of logic.
 2017-07-26 10:21:31 -07:00
Andrew Waterman
5a5b78b15e Improve L2 TLB coding style 2017-07-26 02:22:43 -07:00
Andrew Waterman
5a9c673f41 Fix L2 TLB response bug 
Sometimes, it would inform the L1 TLB that the translation was for
a superpage, even though that's never the case.
 2017-07-26 02:20:41 -07:00
Andrew Waterman
acca0fccf5 Fix BTB not being refilled on some indirect jumps 
We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB.  That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to.  This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow.  Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.

This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
 2017-07-26 02:13:43 -07:00
Yunsup Lee
6916e5cbfb coreplex: better names for RocketTiles in Verilog (#890) 2017-07-25 16:35:31 -07:00
Andrew Waterman
d43f02268b Merge pull request #889 from freechipsproject/acq-before-rel-and-jump-in-frontend 
Acquire before release; jump in frontend
 2017-07-25 16:26:47 -07:00