riscv/rocket-chip
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Author SHA1 Message Date
Henry Cook
dd5052888d refactor tilelink params, compiles but ExampleSmallConfig fails 2015-10-13 23:44:05 -07:00
Howard Mao
a44e054c77 add support for different TileLink and MIF data widths 2015-10-13 12:46:23 -07:00
Henry Cook
9d11b64c75 added HasAddrMapParameters and GlobalAddrMap 2015-10-06 18:24:08 -07:00
Henry Cook
1c489d75c1 inject params at top-level for MemDessert 2015-10-06 16:26:58 -07:00
Henry Cook
c4eadbda57 Removed all traces of params 2015-10-06 11:42:06 -07:00
Henry Cook
38ae2707a3 refactor MemIO to not use params 2015-10-06 11:41:48 -07:00
Henry Cook
3d10a89907 refactor NASTI to not use param; new AddrMap class 2015-10-06 11:41:47 -07:00
Andrew Waterman
c2ad0b7dd4 Unfuck fpga-zynq submodule pointer 
Sorry, Scott.
 2015-10-01 15:00:35 -07:00
Andrew Waterman
996670a4a6 Point to correct Chisel commit 2015-10-01 10:31:29 -07:00
Howard Mao
a76f0bf8fb fix involuntary release bug in rocket ProbeUnit 2015-09-30 17:26:48 -07:00
Andrew Waterman
8da7be3211 More Chisel3 compatibility fixes 2015-09-30 14:37:40 -07:00
Andrew Waterman
79cdf6efc0 Make perf counters optional 2015-09-28 13:56:08 -07:00
Howard Mao
353b00c8a1 revert some Chisel3-related changes and fix tlb bugs 2015-09-26 22:08:06 -07:00
Howard Mao
c517d9f6e3 fix htif emulator constructor in vcs_main 2015-09-25 17:21:09 -07:00
Howard Mao
7b0167b92e make sure SCR and PCR data width matches xLen 2015-09-25 12:13:22 -07:00
Howard Mao
0e67d824b4 fix NASTI interconnect bug 2015-09-25 12:12:34 -07:00
Howard Mao
0d763524ef make sure conf address map scales with number of cores 2015-09-25 09:41:19 -07:00
Howard Mao
5e3f9115d3 make sure HTIF mem_mb doesn't exceed MMIOBase 2015-09-25 09:02:35 -07:00
Schuyler Eldridge
f200d0947a Force C++ emulator to always use 1GB for MEM_SIZE 
Fixes #17
 2015-09-24 23:56:41 -04:00
Howard Mao
c20ed350a0 even more Chisel3 compatability changes 2015-09-24 17:55:41 -07:00
Howard Mao
1c0111cc70 uncore merge commit 2015-09-24 17:10:45 -07:00
Howard Mao
8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:59:13 -07:00
Howard Mao
4a85c5a510 pull in hardfloat fixes 2015-09-24 16:58:49 -07:00
Scott Beamer
fbc6e695d3 remove bugs from float_fix 2015-09-23 16:11:47 -07:00
Scott Beamer
56daea793a allow float_fix to take stdin (for piping) 2015-09-23 16:09:09 -07:00
Howard Mao
38a9b23ce7 add a flag to only log and dump after a certain number of cycles 2015-09-22 10:32:31 -07:00
Howard Mao
4496e8d4e2 make sure htif_emulator properly sets memory size 2015-09-22 10:32:31 -07:00
Howard Mao
56ecdff52d Implement NASTI-based Mem/IO interconnect 2015-09-22 10:32:31 -07:00
Andrew Waterman
c6bcc832a1 Chisel3: Don't use Vec.fill for IOs 2015-09-20 13:43:56 -07:00
Andrew Waterman
fd58c52250 Update to latest chisel 2015-09-20 13:37:53 -07:00
Colin Schmidt
6f85ed191e Add rocketchip_addons to the list of chisel srcs requiring rebuild 2015-09-16 12:28:03 -07:00
Colin Schmidt
7ecb936bf5 Remove -j from "make run-bmark-tests" in travis 
+currently causes inconsistency in build success
+unclear what root cause is
 2015-09-16 12:27:05 -07:00
Scott Beamer
de81762f7c faster and more conservative float_fix 2015-09-15 17:19:29 -07:00
Scott Beamer
7e25b1ce03 cleaner/faster comlog without linear search 2015-09-15 17:19:29 -07:00
Christopher Celio
754c47bdd1 Removed "make debug" test from travis 
- currently causes gcc4.8 to crash
  - likely due to high memory requirements in compiling generated c++
    code for debug/vcd output
 2015-09-14 15:45:50 -07:00
Colin Schmidt
d355d81633 regression script bump for new torture that can produce waveforms 2015-09-14 13:00:54 -07:00
Scott Beamer
3eed7ff238 make float_fix more conservative with replacement 2015-09-12 11:00:00 -07:00
Scott Beamer
a12cd13190 tool to unrecode single floats from commit logs 2015-09-11 20:19:18 -07:00
Christopher Celio
c2344ee2bc Added generated-src-debug to make clean target 2015-09-11 19:07:33 -07:00
Christopher Celio
c9d89226fb Generated *.d file of tests now kept in order 
-Changed Set to LinkedHashSet in Testing.scala
 2015-09-11 18:36:04 -07:00
Christopher Celio
c8a7deb950 Added a commitlog post-processor for Rocket 
- Useful for taking Rocket's out-of-order writebacks and generating an
    in-order commit log.
  - Resulting commit log can be diffed against Spike's commit log.
 2015-09-11 16:06:01 -07:00
Christopher Celio
17e971bbfa Add emulator "make debug" and "-j" to travis 2015-09-10 17:34:16 -07:00
Christopher Celio
d9a2162472 Bump Chisel 2015-09-10 17:26:41 -07:00
Christopher Celio
8f71c4da2d Reintroduced multiple emulator backend directories 
Fixes a "make -j" concurrency bug due to deleting files that another
  parallel rule depends on.
 2015-09-10 17:14:23 -07:00
Christopher Celio
83df4bcc35 Fixed run-bmark-tests make target in vsim 2015-09-09 22:37:47 -07:00
Colin Schmidt
af7336ef8b blacklist private branches from travis 2015-09-08 15:13:38 -07:00
Andrew Waterman
d08b75c472 Merge pull request #15 from ucb-bar/fix_disasm_garbage 
If you don't have spike-disasm in your path, your path is dumped
 2015-09-03 17:55:31 -07:00
Ben Keller
8e9c15c10d If you don't have spike-disasm in your path, your path is dumped 
to stdout by this line every time you do anything in the entire repo.
 2015-09-03 15:36:11 -07:00
Christopher Celio
e6b6ff5a1d Update README.md 
Corrected PublicConfigs.scala -> Configs.scala
 2015-09-02 22:55:53 -07:00
Colin Schmidt
1bfd873888 bump chisel version for seqmem setname 2015-08-29 12:53:57 -07:00