Rimas Avizienis
|
82a636ff55
|
AMOADD, AMOAND, AMOOR, AMOSWAP working
|
2011-11-15 00:51:45 -08:00 |
|
Rimas Avizienis
|
48cec01710
|
updated riscv-bmarks and riscv-tests to build with new toolchain
|
2011-11-15 00:11:22 -08:00 |
|
Rimas Avizienis
|
9d3471a569
|
more cache fixes, more test harness debug output
|
2011-11-13 23:32:18 -08:00 |
|
Rimas Avizienis
|
67c7e7e28f
|
cache/tlb bugfixes, increased memory size to 256meg
|
2011-11-13 13:06:35 -08:00 |
|
Rimas Avizienis
|
5f4b15b809
|
added ld/st misaligned exceptions
|
2011-11-13 00:03:17 -08:00 |
|
Rimas Avizienis
|
35af912bd2
|
cache optimizations, cleanup, and testharness improvement
|
2011-11-12 22:13:29 -08:00 |
|
Rimas Avizienis
|
91c252ad08
|
fixing output enable signals for data/tag SRAMs
|
2011-11-12 15:47:47 -08:00 |
|
Rimas Avizienis
|
83d90c4dab
|
more itlb/dtlb/ptw fixes
|
2011-11-12 15:00:45 -08:00 |
|
Rimas Avizienis
|
73416f224b
|
more tlb/ptw debugging
|
2011-11-12 00:25:06 -08:00 |
|
Rimas Avizienis
|
a1ce908541
|
dcache/dtlb overhaul
|
2011-11-11 18:18:47 -08:00 |
|
Rimas Avizienis
|
f86d5b1334
|
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
|
2011-11-10 11:26:13 -08:00 |
|
Rimas Avizienis
|
9aca403aa8
|
more itlb integration & cleanup
|
2011-11-09 23:18:14 -08:00 |
|
Rimas Avizienis
|
e96430d862
|
integrating ITLB & PTW
|
2011-11-09 14:52:17 -08:00 |
|
Rimas Avizienis
|
9d63087eb2
|
changed caches to use separate sram modules for tag and data arrays
|
2011-11-07 00:58:25 -08:00 |
|
Rimas Avizienis
|
4d64099103
|
cleanup
|
2011-11-04 20:52:21 -07:00 |
|
Rimas Avizienis
|
4459935554
|
dcache fixes - all tests and ubmarks pass, hello world still broken
|
2011-11-04 15:40:41 -07:00 |
|
Rimas Avizienis
|
7a528d6255
|
fixes for div/mul hazard checking + cleanup
|
2011-11-01 23:14:34 -07:00 |
|
Rimas Avizienis
|
3b3d988fde
|
dcache loads working - 1/2 cycle load/use delay depending on load type
|
2011-11-01 21:25:52 -07:00 |
|
Rimas Avizienis
|
08b89e7710
|
interface cleanup, major pipeline changes
|
2011-11-01 17:59:27 -07:00 |
|
Rimas Avizienis
|
ace4c9d13c
|
dcache fixes
|
2011-10-31 17:17:36 -07:00 |
|
Rimas Avizienis
|
65f8b2461c
|
dcache tweaks
|
2011-10-31 16:47:31 -07:00 |
|
Rimas Avizienis
|
172e561a78
|
added once cycle latency store pipelined d$
|
2011-10-31 15:37:37 -07:00 |
|
Rimas Avizienis
|
c06e2d16e4
|
initial commit of rocket chisel project, riscv assembly tests and benchmarks
|
2011-10-25 23:02:47 -07:00 |
|