Andrew Waterman
71205b70cc
Make RocketTileWrapper a BaseTile
2017-10-07 17:36:24 -07:00
Henry Cook
8da7aabd51
tile: supply hartid from RocketTileParams
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make WithNCores partial configs override rather than append more tiles
2017-10-05 00:31:53 -07:00
Henry Cook
45581e60f0
Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"
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This reverts commit 5232a29d7d
, reversing
changes made to a2dc13669a
.
2017-10-05 00:26:44 -07:00
Andrew Waterman
32fda51a2c
Get rid of paddrBits from SystemBus ( #1029 )
2017-10-04 12:11:37 -07:00
Henry Cook
cedfb0e784
coreplex: dontTouch the rocket_tile_inputs wire
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which contains hartid.
2017-10-02 19:36:10 -07:00
Wesley W. Terpstra
0a287df0f7
Merge remote-tracking branch 'origin/master' into auto-diplomacy-bundles
2017-09-27 16:28:10 -07:00
Wesley W. Terpstra
9307092d14
coreplex: draw the FrontBus at the bottom and SystemBus at the top
2017-09-27 14:20:39 -07:00
Wesley W. Terpstra
e07d86aecd
rocket: flip interrupt rendering so cores are on top
2017-09-27 12:46:29 -07:00
Wesley W. Terpstra
1fda05970a
rocket: move interrupt synchronizers to correct side of crossing
2017-09-27 12:33:08 -07:00
Wesley W. Terpstra
0268959c24
rocket: move interrupt synchronizers to correct side of crossing
2017-09-27 12:02:04 -07:00
Wesley W. Terpstra
5af08966d8
coreplex: fix WithoutTLMonitors
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closes #1017
2017-09-27 00:57:18 -07:00
Wesley W. Terpstra
31a934bec0
coreplex: buses are now LazyModules with LazyScope
2017-09-26 14:58:56 -07:00
Wesley W. Terpstra
a27e853101
diplomacy: move rendering properties to edges
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FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
2017-09-26 13:24:36 -07:00
Henry Cook
9d5e96672e
coreplex: clean up coherence manager attachment point
2017-09-25 18:07:51 -07:00
Wesley W. Terpstra
b9a2e4c243
diplomacy: API beautification
2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
9217baf9d4
diplomacy: change API to auto-create node bundles => cross-module refs
2017-09-22 15:01:39 -07:00
Wesley W. Terpstra
17ba209ed0
coreplex: name LazyModules
2017-09-22 14:38:47 -07:00
Andrew Waterman
afad25fceb
Integrate L1 BusErrorUnit
2017-09-20 00:05:07 -07:00
Henry Cook
56dae946b6
coreplex: MemoryBusParams.beatBytes also based on XLen
2017-09-13 11:25:42 -07:00
Henry Cook
b86f4b9bb7
config: use Field defaults over Config defaults
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Also rename some keys that had the same class name as their value's class name.
2017-09-13 11:25:42 -07:00
Henry Cook
a7540d35b7
ports: use BigInts instead of Longs and the new x"..." context
2017-09-13 11:25:42 -07:00
Henry Cook
9c0bfbd500
tile: remove global Field ResetVectorBits
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Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
2017-09-08 14:50:59 -07:00
Henry Cook
e46aeb7342
tile: remove PAddrBits in favor of SharedMemoryTLEdge
2017-09-08 13:53:36 -07:00
Wesley W. Terpstra
e723a3f42b
MemoryBus: fanout the A for performance
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
a450357744
tilelink: Monitor construction method is unconditional
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Whether or not a Monitor should be placed is decided by diplomacy.
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1a87ed1193
coreplex: add externalSlaveBuffers configuration option
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
fd8a51a910
coreplex: rename externalBuffers to externalMasterBuffers
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
b1cacc56ad
SystemBus: restore correct order of FIFOFixer and Buffer
2017-09-05 16:41:39 -07:00
Wesley W. Terpstra
b74a419bfb
FrontBus: FIFOFixer should not have a buffer between it and Xbar
2017-09-05 16:27:57 -07:00
Wesley W. Terpstra
e65f49b89a
FrontBus: attach to splitter for cross-chip visibility
2017-09-05 15:03:41 -07:00
Wesley W. Terpstra
5886025b1a
sbus => pbus: 2 buffers should already be enough
...
There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.
Between them is only an AtomicAutomata.
That should be enough for most designs.
2017-09-05 15:03:38 -07:00
Henry Cook
a902e15987
pbus: clarify that we are adding buffers when attaching to sbus
2017-09-05 15:03:38 -07:00
Henry Cook
8fc4d78c84
frontbus: provide fifofixer on the side of the front bus where masters connect
2017-09-05 15:03:38 -07:00
Megan Wachs
667d966410
TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming
2017-09-05 15:03:38 -07:00
Megan Wachs
94f06dc85c
pbus: turn down overkill buffering between PBus and SBus
2017-09-05 15:03:38 -07:00
Henry Cook
3bde9506c6
coreplex: allow buffer chains on certain bus ports
2017-09-05 15:03:36 -07:00
Megan Wachs
57d0360c35
frontbus: Name the connection.
2017-08-30 18:07:34 -07:00
Megan Wachs
c99afe4c66
buses: Name all the things.
2017-08-30 17:31:42 -07:00
Henry Cook
32cb358c81
coreplex: include optional tile name for downstream name stabilization
2017-08-30 15:48:55 -07:00
Megan Wachs
183fefb2b9
Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in
2017-08-30 15:27:56 -07:00
Wesley W. Terpstra
d5b62dffda
SystemBus: add stupidly many (4 more) buffers from sbus=>pbus
...
This should probably be reverted.
2017-08-30 14:22:49 -07:00
Henry Styles
f7330028cc
Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter
2017-08-30 14:22:49 -07:00
Wesley W. Terpstra
656609d610
SystemBus: split FIFOFixers along bus boundaries
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If you have a system with a lot of periphery slaves, you wan to FIFO fix
them on the periphery bus rather than paying the circuit cost at the sbus.
2017-08-30 13:28:11 -07:00
Wesley W. Terpstra
bf19440db5
SystemBus: use a full buffer on slaves
2017-08-26 02:47:04 -07:00
Megan Wachs
103b6bc6d3
systemBus: allowing naming the TLBuffers which get inserted
2017-08-24 14:49:12 -07:00
Wesley W. Terpstra
17134125e1
SystemBus: remove misnamed functions ( #972 )
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These functions were actually for cross connecting chips.
2017-08-24 23:35:01 +02:00
Henry Cook
2910d6fa2a
tilelink: make bus xbar protected so it can be suggestNamed
2017-08-07 17:30:24 -07:00
Henry Cook
c457c9cb9f
tilelink: allow insertion of TLDelayer on TLBus outward node
2017-08-07 16:43:06 -07:00
Yunsup Lee
6ef8ee5d4d
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
Wesley W. Terpstra
13d3ffbcaa
tilelink: Filter now support arbitrary filter functions
2017-07-31 16:38:38 -07:00
Wesley W. Terpstra
540256e24a
systembus: all slaves should have an output buffer
2017-07-29 00:13:33 -07:00
Wesley W. Terpstra
68064ba260
systembus: don't double down on buffers
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The order should be:
master => buffer|xing => fifofixer => splitter => xbar
2017-07-29 00:02:12 -07:00
Henry Cook
7eeb9dfd88
Merge pull request #899 from freechipsproject/wrapper-dedup
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Stabilize tile wrappers for downstream tools
2017-07-28 10:52:59 -07:00
Wesley W. Terpstra
2e4f1611ed
tilelink: Error device supports Acquire
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We need this if we want to divert traffic to it from a TL-C slave.
2017-07-27 18:32:58 -07:00
Henry Cook
289ef30dbc
coreplex: change AsynchronousCrossing.sync default to 3
2017-07-27 15:44:51 -07:00
Henry Cook
9a483af6e8
coreplex: naming of tile wrappers
2017-07-27 15:16:48 -07:00
Henry Cook
33852ef965
coreplex: remove superfluous sink and source from wrapper
2017-07-27 14:23:03 -07:00
Yunsup Lee
6916e5cbfb
coreplex: better names for RocketTiles in Verilog ( #890 )
2017-07-25 16:35:31 -07:00
Yunsup Lee
c9e467a668
coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency ( #887 )
2017-07-25 00:55:55 -07:00
Wesley W. Terpstra
68ed055f6d
chiplink: adjust bus view to include the splitter ( #886 )
2017-07-24 21:41:17 -07:00
Yunsup Lee
dc435af30a
fix HasRTCModuleImp ( #885 )
2017-07-24 20:24:59 -07:00
Henry Cook
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
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* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
Wesley W. Terpstra
4eface8a9e
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
Henry Cook
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
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* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
Wesley W. Terpstra
bca3db0866
diplomacy: add RWXC permissions also to ResourceMappings
2017-06-28 15:06:19 -07:00
Colin Schmidt
aced18b3bb
Move RoCC interface to Diplomacy and TL2 ( #807 )
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* Move RoCC interface to Diplomacy and TL2
* guard rocc arbiter to prevent zero-width wires
2017-06-22 12:07:09 -07:00
Wesley W. Terpstra
2f2fe0a973
clint: don't ask for what you know (nTiles)
2017-06-20 17:21:53 -07:00
Henry Cook
1c97a2a94c
allow re-positionable PLIC and Clint, and change coreplex internal network names
2017-06-20 17:18:45 -07:00
Henry Cook
5368ea60fe
Merge pull request #757 from freechipsproject/isp-port
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Inter-System-Port
2017-06-15 13:07:19 -07:00
Wesley W. Terpstra
1f8c4ba4ca
CoreplexNetwork: don't force a buffer on the coherence manager
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Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
2017-06-14 14:27:23 -07:00
Wesley W. Terpstra
b1917e7915
coreplex: add an ISPPort trait to add cross-connect points
2017-06-02 20:43:23 -07:00
Wesley W. Terpstra
81d372137a
coreplex: unconditionally insert a Splitter between tiles and l1tol2
2017-06-02 20:43:21 -07:00
Wesley W. Terpstra
475ac93cdf
coreplex: print memory map using DTS, also write a JSON for it
2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
5994714970
diplomacy: move manager unification to meta-data only
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Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
2017-06-01 15:30:20 -07:00
Yunsup Lee
6124bf0cc2
sort entires in the printed address map ( #773 )
2017-05-31 07:45:46 -10:00
Megan Wachs
d8996ea85f
Empty commit to force travis
2017-05-16 22:56:58 -07:00
Henry Cook
5f22e91a7f
rocc: fix RoccExampleConfig
2017-05-16 16:44:53 -07:00
Wesley W. Terpstra
b4188ee625
axi4: ToTL supporting pipelined MMIO
2017-05-01 22:53:40 -07:00
Megan Wachs
d67738204f
Interrupts: Less Pessimistic Synchronization ( #714 )
...
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.
* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC
* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.
* interrupts: use consistent async/periph/core ordering
* interrupts: Properly condition on 0 External interrupts
* interrupts: CLINT is also synchronous to periph clock
2017-04-28 14:49:24 -07:00
Henry Cook
3d0ed80ef6
new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels
2017-04-27 18:17:31 -07:00
Henry Cook
bdb526a9f0
coreplex: DefaultCoreplex => RocketPlex
2017-04-27 18:17:09 -07:00
Wesley W. Terpstra
b4d17c76d1
coreplex: make rational+synchronous crossing configurable ( #688 )
2017-04-19 16:16:05 -07:00
Megan Wachs
df5caba7bf
debug: Make it easier to override parts of the Default Debug Config ( #655 )
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* Handle single-step with a pipeline stall, not a flush
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
* debug: Make it easier to override parts of the Default Debug Config
* Fix typo in Debug code generation
abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
2017-04-06 10:33:17 -07:00
Megan Wachs
629e9a2ef6
debug: Put DebugROM back inside the overall Debug Module ( #647 )
2017-04-03 16:36:53 -07:00
Megan Wachs
d2c1bdc2ce
Debug Controls ( #639 )
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* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.
* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
2017-04-03 13:31:35 -07:00
Megan Wachs
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
Wesley W. Terpstra
a2fc51d65e
soc: compatible with "simple-bus" => scanned for platform devices
2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253
get local interrupts out of the tile
2017-03-30 00:36:23 -07:00
Megan Wachs
42ca597478
debug: Breaking change until FESVR is updated as well.
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* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
Megan Wachs
08c4f7cea6
RocketTile: Create a wrapper for SyncRocketTile as well ( #616 )
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* RocketTile: Create a wrapper for SyncRocketTile as well
There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.
Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.
Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.
It could still be nice to use a parameter vs hard coding "3".
* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
Wesley W. Terpstra
537274b645
coreplex: move buffers inside the coreplex
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This should make hierarchical place and route easier.
2017-03-24 22:54:48 -07:00
Yunsup Lee
5bbb75e078
rename l2FrontendBus as fsb, expose bsb
2017-03-24 22:54:48 -07:00
Henry Cook
996a31364a
rocket: remove hard-coded paddrBits ( #610 )
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Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
Wesley W. Terpstra
9a2f0d01a1
GenerateBootROM: use compiled DTB
2017-03-24 18:18:01 -07:00
Andrew Waterman
3ea822c2cf
Make blocking L1 D$ the default
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The nonblocking cache is overdesigned for most Rocket-class cores, so
the blocking cache is the more appropriate default.
2017-03-24 16:39:52 -07:00
Wesley W. Terpstra
19eb9b6906
l1tol2: put a flow Q on the exits ( #606 )
...
This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
2017-03-23 16:28:32 -07:00
Wesley W. Terpstra
81d717e82f
coreplex: guarantee FIFO for those tiles that need it
2017-03-21 11:16:51 -07:00
Andrew Waterman
db0a02b78e
WIP on priv-1.10
2017-03-09 11:29:51 -08:00
Henry Cook
d0ae087587
rocket: allow scratchpad address to be configurable ( #570 )
2017-03-06 21:35:45 -08:00
Henry Cook
229fb2251d
coreplex: hack to fix tile dedup ( #569 )
2017-03-06 16:36:03 -08:00