Wesley W. Terpstra
5d70265e86
rocket: L1 only needs cache-line transfer sizes
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
bf7823f1c8
tilelink2: split suportsAcquire into T and B variants
2017-01-19 19:07:13 -08:00
Henry Cook
c1b7c84f09
[rocket] bugfix: RoccExampleConfig looks up PAddrBits too early
2017-01-19 17:48:04 -08:00
Henry Cook
307f938b88
[rocket] bugfix: fixes #517
2017-01-19 17:48:04 -08:00
Henry Cook
74b6a8d02b
Refactor Tile to use cake pattern ( #502 )
...
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
2017-01-16 18:24:08 -08:00
Andrew Waterman
71c4b000b3
Don't special-case power-of-2 replacement policy for BTB
...
PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage. Regardless,
this should be a second-order effect, so using FIFO always is fine.
2017-01-11 13:21:55 -08:00
Henry Cook
540502f96d
Convert frontend and icache to diplomacy/tl2 ( #486 )
...
* [rocket] file capitalization
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
2016-12-12 17:38:55 -08:00
Wesley W. Terpstra
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
...
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
Andrew Waterman
915697cb09
Fix FEQ flag generation ( #479 )
...
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).
Also, minor code cleanup.
2016-12-06 11:54:29 -08:00
Schuyler Eldridge
36fe024671
CacheName no longer needed in RoCCInterface
...
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
2016-12-04 19:01:39 -08:00
Schuyler Eldridge
624db2034b
Make instantiated RoCC use dcacheParams
2016-12-04 19:01:39 -08:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
4146f6a792
TLB: do not access illegal addresses ( #460 )
2016-11-26 15:11:42 -08:00
Wesley W. Terpstra
1e0aca7358
dcache: the high bit of s2_req.typ is the SIGN bit (not size) ( #455 )
2016-11-25 15:26:22 -08:00
Henry Cook
38c5af5bad
[rocket] cleanup mshr logic
2016-11-23 12:09:56 -08:00
Henry Cook
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
Henry Cook
c65c255815
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
Andrew Waterman
5f3fb64ef0
Per ABI, only x1 and x5 should be treated as function returns
...
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
2016-11-22 12:01:05 -08:00
Wesley W. Terpstra
5fe107bb07
rocket: pass scratchpad address to block dcache
2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
c18bc07bbc
TLB: determine RWX from TL2 properties directly
2016-11-21 21:13:26 -08:00
Henry Cook
28c6be90ab
[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
2016-11-20 19:36:51 -08:00
Henry Cook
ff9b5bf8fc
[rocket] nbdcache release bugfix
2016-11-20 19:07:06 -08:00
Henry Cook
3f47d5b5eb
[rocket] re-enable working NBDcache (passes Tracegen)
2016-11-19 19:19:16 -08:00
Colin Schmidt
9dd12545d0
[Rocket] Send correct type for iomshr reqs
...
Also contain grow param bugfix
2016-11-19 19:04:06 -08:00
Wesley W. Terpstra
32a1c27441
rocket: disable nbdcache until it's fully ported
2016-11-18 19:55:24 -08:00
Wesley W. Terpstra
452bb2fc80
dcache fix TinyConfig
2016-11-18 19:50:34 -08:00
Henry Cook
2976fd84e4
[rocket] resolve cde/config conflicts
2016-11-18 19:11:34 -08:00
Henry Cook
8b908465e0
[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
2016-11-18 19:04:06 -08:00
Wesley W. Terpstra
37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
30425d1665
rocketchip: eliminate all Knobs
2016-11-18 14:31:42 -08:00
Henry Cook
5bd343bac8
[rocket] d_last && d.fire() => d_done
2016-11-17 18:42:59 -08:00
Henry Cook
1ddccb1b33
[rocket] add TODO for single cycle ack
2016-11-17 18:42:59 -08:00
Henry Cook
e1992d7c55
[rocket] grant addr bugfix
2016-11-16 18:12:06 -08:00
Henry Cook
da7ecfd189
[rocket] probeack vs probeackdata bugfix
2016-11-16 17:27:02 -08:00
Henry Cook
1f51564577
[rocket] dcache probe ack data bugfix
2016-11-16 14:25:21 -08:00
Henry Cook
66a2c5544e
[rocket] L1D acquire addr bugfix
2016-11-16 13:38:52 -08:00
Henry Cook
c5e03c9c76
[rocket] dcache release addr bugfix
2016-11-16 13:14:51 -08:00
Wesley W. Terpstra
10e459fedb
rocket: change connection between rocketchip and coreplex
...
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
Henry Cook
0e30364f56
WIP
2016-11-14 13:39:01 -08:00
Henry Cook
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
Henry Cook
b7730d66f2
WIP bugfixes: run until corrupted WB data (beats repeated)
2016-11-11 18:34:48 -08:00
Henry Cook
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
Henry Cook
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
92ee498521
rocket scratchpad: support atomics
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
545154c1c3
groundtest: make it happy with TL2 addressing
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
e9725aea2f
rocketchip: all of the address map now comes from TL2
2016-10-31 11:42:44 -07:00
Wesley W. Terpstra
b68bc449e7
rocket: put a Fragmenter infront of the scratchpad
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
11121b6f4c
rocket: convert scratchpad to TL2
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
dddb50a942
BuildTiles: convert to LazyTile
2016-10-31 11:42:13 -07:00
Colin Schmidt
85f3788ab5
initialize s2_hit to solve #401
2016-10-21 14:53:55 -07:00
Andrew Waterman
c22438b822
Fix an overly strict D$ assertion
2016-10-06 15:52:46 -07:00
Andrew Waterman
5980dc160f
Don't allow multiple entries for same PC in BTB
...
Necessary for RVC forward-progress guarantee.
2016-10-06 11:30:45 -07:00
Andrew Waterman
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
Andrew Waterman
67593fdf2d
Explicitly zap some S-mode CSRs when not using S-mode
2016-10-04 22:29:39 -07:00
Andrew Waterman
064c9ebdc6
Don't report I$ fetch faults on TLB misses!
2016-10-04 14:37:25 -07:00
Andrew Waterman
516481b68b
Improve back-to-back integer multiplication performance
...
More exact hazard checking in the decode stage avoids a pipeline flush.
2016-10-04 14:37:25 -07:00
Andrew Waterman
7b69f1f261
Don't enter D$ flush state machine if grant outstanding
2016-10-04 14:37:25 -07:00
Andrew Waterman
28beb33943
Make any intervening load/store/fence fail an LR/SC sequence
...
This catches LR/SC misuses more quickly.
2016-10-04 14:37:25 -07:00
Andrew Waterman
e0188f8aa4
Don't implicitly fence on CSR instructions
...
CSRs that have an effect on I/O should use an explicit FENCE.
2016-10-01 19:44:10 -07:00
Andrew Waterman
b772edcb1b
Allow hit-under-MMIO and multiple MMIOs in blocking D$
...
The latter feature is by default disabled, since there aren't enough
ID bits.
2016-10-01 19:44:05 -07:00
Howard Mao
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Yunsup Lee
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Andrew Waterman
d0572d6aab
Allow reset vector to be set dynamically
...
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins. Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.
Additionally, allow MTVEC to *not* be reset. In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does. So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
Andrew Waterman
e6c1bcfedd
Expose carry-out bits from WideCounter
2016-09-19 15:54:17 -07:00
Andrew Waterman
a49814c667
Allow WideCounter to not be reset
2016-09-18 18:45:51 -07:00
Andrew Waterman
5566bf1b13
Don't route PLIC interrupts through PRCI
...
The PLIC is local to the Coreplex, and PRCI should not be.
2016-09-14 11:01:05 -07:00
Howard Mao
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
Andrew Waterman
61cbe6164d
Add option to execute JAL from decode stage
...
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC. Caveat emptor.
2016-09-13 02:32:00 -07:00
Andrew Waterman
88440ebf89
Use PseudoLRU in BTB when possible (for powers of two)
2016-09-12 16:52:03 -07:00
Andrew Waterman
96185e4b16
tighten an assert condition
...
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
2016-09-12 16:49:46 -07:00
Andrew Waterman
beb141a20b
Allow M, A, D, C extensions to be disabled in misa register
2016-09-12 16:49:46 -07:00
Andrew Waterman
656aa78f7d
Pipeline FMAs more deeply by default
...
Rocket's QoR has improved enough that the FMAs are on the critical
path. This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
2016-09-09 11:06:42 -07:00
Andrew Waterman
eaa4b04ee5
Check D$ store->load collisions more precisely
...
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
2016-09-09 11:06:42 -07:00
Andrew Waterman
a7f47f3c23
Reduce default BTB size
...
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a
. The intent was to
fit the dhrystone working set (rofl) which the new value of 40 does.
2016-09-07 01:51:27 -07:00
Andrew Waterman
9fea4c83da
Add RV32F support
2016-09-07 00:05:39 -07:00
Andrew Waterman
66e9f027e0
Add MuxT to mux on Tuple2 and Tuple3
2016-09-07 00:05:38 -07:00
Andrew Waterman
511cc6c5c5
Evaluate arg to Boolean.option lazily
2016-09-07 00:05:38 -07:00
Andrew Waterman
a0dcd42e80
avoid erroneously setting tags valid during flush
2016-09-07 00:05:38 -07:00
Andrew Waterman
63679bb019
Add support for L1 data scratchpads instead of caches
...
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
Andrew Waterman
c05ba1e864
Add TileId parameter, generalizing GroundTestId
...
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
2016-09-02 00:10:50 -07:00
Howard Mao
c66318307c
no longer need to set invalidate_lr in RoCC examples
2016-08-31 22:05:35 -07:00
Howard Mao
27c674972c
tie off invalidate_lr in RoCC
2016-08-31 22:00:27 -07:00
Howard Mao
bb578494d8
don't override req.bits.phys in SimpleHellaCacheIF
2016-08-31 22:00:27 -07:00
Howard Mao
403cc1c5c4
fix DecoupledTLB to handle misses appropriately
2016-08-31 22:00:27 -07:00
Andrew Waterman
f4524e4c91
Add PML for Boolean.option; use it
2016-08-31 13:43:04 -07:00
Andrew Waterman
07d48df88a
Get rid of FPU RoCC port logic when RoCC not present
...
The previous approach used ex_reg_valid to determine whether to
source data from the FPU or RoCC. Thus, when the RoCC was not
present, it was still creating muxes. Using ex_cp_valid instead
gets rid of them.
2016-08-29 12:59:17 -07:00
Andrew Waterman
f91552a650
Add performance counter support
2016-08-29 12:31:52 -07:00
Andrew Waterman
1e3339e97c
Update breakpoints to match @timsifive's debug spec
2016-08-29 12:31:52 -07:00
Andrew Waterman
33eaf08b60
set missing port direction
...
Ideally, chisel should flag this as an error.
2016-08-29 12:31:52 -07:00
Ben Keller
79293f4fa2
Use a better iterator inside the DCache
2016-08-25 20:41:39 -07:00
Howard Mao
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00