solomatnikov
127f121ef2
Preserve id_do_fence ( #651 )
2017-04-05 08:29:45 -07:00
Andrew Waterman
19f0ae64a0
Only set id_reg_fence when AMO/FENCE is actually executed
...
This is a performance bug, not a correctness bug. But randomly stalling
because of garbage bits coming out of the I$ should be avoided.
h/t @solomatnikov
2017-04-03 21:13:52 -07:00
Andrew Waterman
410e9cf736
I$ bugfix, to be reworked
2017-03-31 12:17:41 -07:00
Henry Cook
b9550e8523
Merge branch 'master' into name-rams
2017-03-30 17:36:01 -07:00
Andrew Waterman
a8a2ee711c
Give I$ RAMs consistent names
2017-03-30 15:50:54 -07:00
Andrew Waterman
2720095b8e
Give D$ RAMs consistent names
2017-03-30 15:49:14 -07:00
Andrew Waterman
70e7e90c02
Remove splitMetadata option from L1 caches
...
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
2017-03-30 15:48:55 -07:00
Megan Wachs
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
Andrew Waterman
fd39eadcd6
New PMP encoding
2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
2f2b472098
rocket: split the interrupt controller into its own node
2017-03-30 00:36:23 -07:00
Andrew Waterman
3546c8d133
If any PMPs are supported, all CSRs exist
2017-03-30 00:36:23 -07:00
Andrew Waterman
8f73a58d90
Report access exception, not page fault, if page-table walk fails
2017-03-30 00:36:23 -07:00
Andrew Waterman
25232070ec
Don't redundantly set resp_ae in PTW
2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253
get local interrupts out of the tile
2017-03-30 00:36:23 -07:00
solomatnikov
0b9fc94421
Assertion for back-to-back uncached and cached ops ( #631 )
2017-03-29 23:07:17 -07:00
Megan Wachs
d8033b20fc
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-29 14:58:04 -07:00
Andrew Waterman
44fb3be7d0
Fix MMIO/cache refill concurrency bug in DCache
...
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
2017-03-28 17:16:29 -07:00
Andrew Waterman
4215f480ef
Write instruction to badaddr on illegal instruction traps
2017-03-28 00:56:14 -07:00
Megan Wachs
bb64c92906
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
Andrew Waterman
05cbdced78
Work around zero-entry vec issue in Chisel
2017-03-27 17:57:26 -07:00
Andrew Waterman
d42d8aaea7
Make SEIP writable
2017-03-27 16:37:09 -07:00
Andrew Waterman
c7c357e716
Add local interrupts to core (but not yet to coreplex)
2017-03-27 16:37:09 -07:00
Andrew Waterman
069858a20c
rocket: separate page faults from physical memory access exceptions
2017-03-27 16:37:09 -07:00
Andrew Waterman
ea0714bfcb
rocket: hard-wire UXL/SXL fields to 0
...
a2a3346e73
2017-03-27 16:37:09 -07:00
Wesley W. Terpstra
75eba294ec
DCache: Release from the correct ID as well
2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
4959771c97
Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N"
...
This reverts commit 0538dc77ce
.
2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
fa7ead6357
Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO"
...
This reverts commit fb6498f2c3
.
2017-03-27 16:30:46 -07:00
Megan Wachs
08c4f7cea6
RocketTile: Create a wrapper for SyncRocketTile as well ( #616 )
...
* RocketTile: Create a wrapper for SyncRocketTile as well
There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.
Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.
Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.
It could still be nice to use a parameter vs hard coding "3".
* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
Andrew Waterman
5d1165c850
Express PMP mask generator using a carry chain
...
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
2017-03-26 14:20:16 -07:00
Henry Cook
996a31364a
rocket: remove hard-coded paddrBits ( #610 )
...
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
Andrew Waterman
17b1ee3037
Default to 8 PMPs; support 0 PMPs
2017-03-24 16:39:52 -07:00
Andrew Waterman
97006ab396
Don't modulate PMP privilege on passsthrough when !usingVM
2017-03-24 16:39:52 -07:00
Andrew Waterman
3f0d2fe826
Instantiate PTW unconditionally
...
This keeps the PMP datapaths intact. The PTW itself will get optimized
away for the !usingVM case.
2017-03-24 16:39:52 -07:00
Andrew Waterman
30415215b8
Don't check for exceptions on ScratchpadSlavePort accesses
2017-03-24 16:39:52 -07:00
Andrew Waterman
ccd5bc9a91
Improve QoR of PMP homogeneity checker
2017-03-24 16:39:52 -07:00
Andrew Waterman
e9cadf29d2
Improve DCache MMIO QoR
...
No need to store the cmd field. From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
2017-03-24 16:39:52 -07:00
Andrew Waterman
fb6498f2c3
Use Reg(Vec) instead of Seq(Reg) for DCache MMIO
2017-03-24 16:39:52 -07:00
Andrew Waterman
0538dc77ce
For D$, use source 0 through N-1 for MMIO, not 1 through N
...
This makes the code a bit cleaner.
2017-03-24 16:39:52 -07:00
Andrew Waterman
3951e57789
Force each TLB entry into its own clock-gate group
...
This ameliorates a PMP critical path.
I can't figure out how to do this without asUInt/asTypeOf.
2017-03-24 16:39:52 -07:00
Andrew Waterman
8d7f1d777e
Fix an embarrassing typo in the PMPHeterogeneityChecker
2017-03-24 16:39:52 -07:00
Andrew Waterman
10c39cb8d6
Disable mprv in D-mode
2017-03-24 16:39:52 -07:00
Andrew Waterman
d3bda9574c
Put page homogeneity checker in PMP
...
Avoids redundancy between ITLB and DTLB
2017-03-24 16:39:52 -07:00
Andrew Waterman
9e05200e51
Don't require that PMP ranges be aligned to access size
...
e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
2017-03-24 16:39:52 -07:00
Andrew Waterman
29e67279ba
add comments
2017-03-24 16:39:52 -07:00
Andrew Waterman
4c8be13a4d
Improve homogeneity circuit QoR
2017-03-24 16:39:52 -07:00
Andrew Waterman
59d6afa132
mideleg/medeleg not present without less-privileged traps
2017-03-24 16:39:52 -07:00
Andrew Waterman
38808f55d5
Share PMP mask gen between I$ and D$
2017-03-24 16:39:52 -07:00
Andrew Waterman
86d84959cf
More WIP on PMP
2017-03-24 16:39:52 -07:00
Andrew Waterman
2888779422
Flush pipeline from WB stage, not MEM
...
Fixes sptbr write -> instruction translation hazard.
2017-03-24 16:39:52 -07:00
Andrew Waterman
44ca3b60ab
Retime PTW response valid bits
...
It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
2017-03-24 16:39:52 -07:00
Andrew Waterman
a03556220c
Default TLB size = 32
...
@davidbiancolin
2017-03-24 16:39:52 -07:00
Andrew Waterman
1875407316
Get TLB permission checks off D$ clock gating critical path
2017-03-24 16:39:52 -07:00
Andrew Waterman
a4164348b4
Expose MXR to S-mode
2017-03-24 16:39:52 -07:00
Andrew Waterman
0380aed329
PUM -> SUM
2017-03-24 16:39:52 -07:00
Andrew Waterman
29414f3a23
Simplify interrupt-stack discipline
...
f2ed45b179
2017-03-24 16:39:52 -07:00
Andrew Waterman
723352c3e2
Mitigate some more PMP critical paths
2017-03-24 16:39:52 -07:00
Andrew Waterman
7484f27ed3
Don't gate exception-cause pipeline registers separately
...
They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
2017-03-24 16:39:52 -07:00
Andrew Waterman
487b8db5ef
Address some PMP critical paths
2017-03-24 16:39:52 -07:00
Andrew Waterman
03fb334c4c
Take mprv calculation off critical path
2017-03-24 16:39:52 -07:00
Andrew Waterman
f0796f0509
Pass correct access size information to PMP checker
2017-03-24 16:39:52 -07:00
Andrew Waterman
a6874c03f7
Remove DecoupledTLB
2017-03-24 16:39:52 -07:00
Andrew Waterman
78f9f6b9ef
When SFENCE.VMA has rs2 != x0, don't flush global mappings
2017-03-24 16:39:52 -07:00
Andrew Waterman
1b950128e1
PTW should always use S-mode privilege
...
If an exception occurs while a page-table walk is coincidentally in
progress (e.g., an illegal instruction executes during data TLB refill),
then the processor might enter M-mode. However, the PTW's accesses
should proceed without M privilege, to avoid bypassing PMPs.
Note, the same argument doesn't apply to the nonblocking cache's replay
queues, because those accesses have already been checked against the PMPs.
The cache correctly ignores access exceptions reported on replays,
provided no exceptions were reported on the initial access.
2017-03-24 16:39:52 -07:00
Andrew Waterman
aace526857
WIP on PMP
2017-03-24 16:39:52 -07:00
Andrew Waterman
b1b405404d
Set PRV=M when entering debug mode
...
Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
2017-03-24 16:39:52 -07:00
Andrew Waterman
cf168e419b
Support SFENCE.VMA rs1 argument
...
This one's a little invasive. To flush a specific entry from the TLB, you
need to reuse its CAM port. Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.
This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation). It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
2017-03-24 16:39:52 -07:00
Henry Cook
055b8ba1f0
rocket: avoid LinkedHashMap.keys to preserve traversal order ( #603 )
2017-03-22 14:38:33 -07:00
Andrew Waterman
3609254e4a
There's no structural hazard on MMIO store responses
...
So don't stall as though there were.
2017-03-21 14:17:32 -07:00
Yunsup Lee
5eae7e1da4
make DCache s1_nack less conservative for pipelined MMIO requests
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
4c00066746
rocket: describe dcache as two clients (fifo+cached)
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
278f6fea24
tilelink2: define is{Request,Response} based on spec
2017-03-20 13:41:02 -07:00
Wesley W. Terpstra
0c92283a61
rocket icache: tie off b ready
2017-03-19 17:18:50 -07:00
Andrew Waterman
d6f571cbbb
Implement mstatus.TSR
2017-03-13 14:50:06 -07:00
Andrew Waterman
1fea0460ba
Support superpage entries in TLB
2017-03-13 14:50:06 -07:00
Andrew Waterman
2d267b4940
Support corner cases in TLBPermissions
...
Don't crap out if the yes-set or no-set is empty.
2017-03-13 14:50:06 -07:00
Wesley W. Terpstra
c847559853
TLB: add a helper API to determine homogeneous page permissions
2017-03-13 14:50:06 -07:00
Henry Cook
dbc8f4b30b
last => done
2017-03-10 15:58:38 -08:00
Andrew Waterman
380c10f7bd
Zap conflicting TLB entries, preparing for superpage support
...
Superpages create the possibility that two entries in the TLB may match.
This corresponds to a software bug, but we can't return complete garbage;
we must return either the old translation or the new translation. This
isn't compatible with the Mux1H approach. So, flush the TLB and report
a miss on duplicate entries.
2017-03-10 15:58:23 -08:00
Andrew Waterman
b24c43badb
Don't double-count release traffic in perfctrs
2017-03-09 16:49:02 -08:00
Andrew Waterman
4f8f05d635
Add performance counter facility
2017-03-09 13:58:50 -08:00
Andrew Waterman
24a2278fc4
Perform all illegal-instruction detection in ID stage
...
This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
2017-03-09 11:29:51 -08:00
Andrew Waterman
7668827741
Support unrolling the integer divider
2017-03-09 11:29:51 -08:00
Andrew Waterman
74d8d672bf
Improve BTB critical path at slight accuracy cost
...
Make entries fully associative on lower 14 bits only, not full address.
2017-03-09 11:29:51 -08:00
Andrew Waterman
11c8857b5d
Don't re-read I$ RAMs on stall
2017-03-09 11:29:51 -08:00
Andrew Waterman
db0a02b78e
WIP on priv-1.10
2017-03-09 11:29:51 -08:00
Wesley W. Terpstra
43dea38ee9
dcache: we need the bits within the beat so select the right word ( #575 )
...
We now have confirmation that it fixed the problem.
2017-03-08 00:19:09 -08:00
Henry Cook
d0ae087587
rocket: allow scratchpad address to be configurable ( #570 )
2017-03-06 21:35:45 -08:00
Wesley W. Terpstra
676974281a
rocket: describe dcache scratchpad as memory
2017-03-03 02:54:48 -08:00
Wesley W. Terpstra
8e4f348dda
rocket: if no MMU, don't print it in DTS
2017-03-03 00:48:26 -08:00
Wesley W. Terpstra
4535de2669
rocket: use diplomatic interrupts
...
This makes it possible for the PLIC to work with heterogenous cores.
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
5bd9f18e5b
rocket: add dts cpu description
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
fd972f5c67
icache: back-pressure is unnecessary ( #564 )
...
* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
2017-02-24 21:01:56 -08:00
Wesley W. Terpstra
3931b0faff
coreplex: assume L1 runs no slower than L2
2017-02-17 15:15:41 +01:00
Henry Cook
e8c8d2af71
Heterogeneous Tiles ( #550 )
...
Fundamental new features:
* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.
Additional changes that got rolled in along the way:
* rocket: Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
2017-02-09 13:59:09 -08:00
Andrew Waterman
8225676a86
For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN
...
See https://github.com/riscv/riscv-isa-sim/issues/76
2017-02-02 11:55:08 -08:00
Andrew Waterman
75edf42323
Set xPIE=1 on xRET
...
We were setting xPIE=0 instead. This is a benign bug, but still a bug.
2017-02-02 11:55:08 -08:00
Wesley W. Terpstra
9ca8f514c0
rocket: creating Bundles in an object also break dedup!
2017-01-31 14:45:11 -08:00
Wesley W. Terpstra
e5af59db68
rocketchip: work-around ucb-bar/chisel3#472
2017-01-31 14:20:02 -08:00
Wesley W. Terpstra
972953868c
uncore: switch to new diplomacy Node API
...
Most adapters should work on multiple ports.
This patch changes them all.
2017-01-29 15:54:45 -08:00
Wesley W. Terpstra
03f2fe02ac
coreplex: support rational crossing to L2 ( #534 )
2017-01-27 17:09:43 -08:00
Wesley W. Terpstra
5d70265e86
rocket: L1 only needs cache-line transfer sizes
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
bf7823f1c8
tilelink2: split suportsAcquire into T and B variants
2017-01-19 19:07:13 -08:00
Henry Cook
c1b7c84f09
[rocket] bugfix: RoccExampleConfig looks up PAddrBits too early
2017-01-19 17:48:04 -08:00
Henry Cook
307f938b88
[rocket] bugfix: fixes #517
2017-01-19 17:48:04 -08:00
Henry Cook
74b6a8d02b
Refactor Tile to use cake pattern ( #502 )
...
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
2017-01-16 18:24:08 -08:00
Andrew Waterman
71c4b000b3
Don't special-case power-of-2 replacement policy for BTB
...
PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage. Regardless,
this should be a second-order effect, so using FIFO always is fine.
2017-01-11 13:21:55 -08:00
Henry Cook
540502f96d
Convert frontend and icache to diplomacy/tl2 ( #486 )
...
* [rocket] file capitalization
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
2016-12-12 17:38:55 -08:00
Wesley W. Terpstra
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
...
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
Andrew Waterman
915697cb09
Fix FEQ flag generation ( #479 )
...
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).
Also, minor code cleanup.
2016-12-06 11:54:29 -08:00
Schuyler Eldridge
36fe024671
CacheName no longer needed in RoCCInterface
...
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
2016-12-04 19:01:39 -08:00
Schuyler Eldridge
624db2034b
Make instantiated RoCC use dcacheParams
2016-12-04 19:01:39 -08:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
4146f6a792
TLB: do not access illegal addresses ( #460 )
2016-11-26 15:11:42 -08:00
Wesley W. Terpstra
1e0aca7358
dcache: the high bit of s2_req.typ is the SIGN bit (not size) ( #455 )
2016-11-25 15:26:22 -08:00
Henry Cook
38c5af5bad
[rocket] cleanup mshr logic
2016-11-23 12:09:56 -08:00
Henry Cook
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
Henry Cook
c65c255815
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
Andrew Waterman
5f3fb64ef0
Per ABI, only x1 and x5 should be treated as function returns
...
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
2016-11-22 12:01:05 -08:00
Wesley W. Terpstra
5fe107bb07
rocket: pass scratchpad address to block dcache
2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
c18bc07bbc
TLB: determine RWX from TL2 properties directly
2016-11-21 21:13:26 -08:00
Henry Cook
28c6be90ab
[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
2016-11-20 19:36:51 -08:00
Henry Cook
ff9b5bf8fc
[rocket] nbdcache release bugfix
2016-11-20 19:07:06 -08:00
Henry Cook
3f47d5b5eb
[rocket] re-enable working NBDcache (passes Tracegen)
2016-11-19 19:19:16 -08:00
Colin Schmidt
9dd12545d0
[Rocket] Send correct type for iomshr reqs
...
Also contain grow param bugfix
2016-11-19 19:04:06 -08:00
Wesley W. Terpstra
32a1c27441
rocket: disable nbdcache until it's fully ported
2016-11-18 19:55:24 -08:00
Wesley W. Terpstra
452bb2fc80
dcache fix TinyConfig
2016-11-18 19:50:34 -08:00
Henry Cook
2976fd84e4
[rocket] resolve cde/config conflicts
2016-11-18 19:11:34 -08:00
Henry Cook
8b908465e0
[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
2016-11-18 19:04:06 -08:00
Wesley W. Terpstra
37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
30425d1665
rocketchip: eliminate all Knobs
2016-11-18 14:31:42 -08:00
Henry Cook
5bd343bac8
[rocket] d_last && d.fire() => d_done
2016-11-17 18:42:59 -08:00
Henry Cook
1ddccb1b33
[rocket] add TODO for single cycle ack
2016-11-17 18:42:59 -08:00
Henry Cook
e1992d7c55
[rocket] grant addr bugfix
2016-11-16 18:12:06 -08:00
Henry Cook
da7ecfd189
[rocket] probeack vs probeackdata bugfix
2016-11-16 17:27:02 -08:00
Henry Cook
1f51564577
[rocket] dcache probe ack data bugfix
2016-11-16 14:25:21 -08:00
Henry Cook
66a2c5544e
[rocket] L1D acquire addr bugfix
2016-11-16 13:38:52 -08:00
Henry Cook
c5e03c9c76
[rocket] dcache release addr bugfix
2016-11-16 13:14:51 -08:00
Wesley W. Terpstra
10e459fedb
rocket: change connection between rocketchip and coreplex
...
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
Henry Cook
0e30364f56
WIP
2016-11-14 13:39:01 -08:00
Henry Cook
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
Henry Cook
b7730d66f2
WIP bugfixes: run until corrupted WB data (beats repeated)
2016-11-11 18:34:48 -08:00
Henry Cook
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
Henry Cook
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
92ee498521
rocket scratchpad: support atomics
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
545154c1c3
groundtest: make it happy with TL2 addressing
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
e9725aea2f
rocketchip: all of the address map now comes from TL2
2016-10-31 11:42:44 -07:00
Wesley W. Terpstra
b68bc449e7
rocket: put a Fragmenter infront of the scratchpad
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
11121b6f4c
rocket: convert scratchpad to TL2
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
dddb50a942
BuildTiles: convert to LazyTile
2016-10-31 11:42:13 -07:00
Colin Schmidt
85f3788ab5
initialize s2_hit to solve #401
2016-10-21 14:53:55 -07:00
Andrew Waterman
c22438b822
Fix an overly strict D$ assertion
2016-10-06 15:52:46 -07:00
Andrew Waterman
5980dc160f
Don't allow multiple entries for same PC in BTB
...
Necessary for RVC forward-progress guarantee.
2016-10-06 11:30:45 -07:00
Andrew Waterman
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
Andrew Waterman
67593fdf2d
Explicitly zap some S-mode CSRs when not using S-mode
2016-10-04 22:29:39 -07:00
Andrew Waterman
064c9ebdc6
Don't report I$ fetch faults on TLB misses!
2016-10-04 14:37:25 -07:00
Andrew Waterman
516481b68b
Improve back-to-back integer multiplication performance
...
More exact hazard checking in the decode stage avoids a pipeline flush.
2016-10-04 14:37:25 -07:00
Andrew Waterman
7b69f1f261
Don't enter D$ flush state machine if grant outstanding
2016-10-04 14:37:25 -07:00
Andrew Waterman
28beb33943
Make any intervening load/store/fence fail an LR/SC sequence
...
This catches LR/SC misuses more quickly.
2016-10-04 14:37:25 -07:00
Andrew Waterman
e0188f8aa4
Don't implicitly fence on CSR instructions
...
CSRs that have an effect on I/O should use an explicit FENCE.
2016-10-01 19:44:10 -07:00
Andrew Waterman
b772edcb1b
Allow hit-under-MMIO and multiple MMIOs in blocking D$
...
The latter feature is by default disabled, since there aren't enough
ID bits.
2016-10-01 19:44:05 -07:00
Howard Mao
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Yunsup Lee
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Andrew Waterman
d0572d6aab
Allow reset vector to be set dynamically
...
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins. Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.
Additionally, allow MTVEC to *not* be reset. In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does. So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
Andrew Waterman
e6c1bcfedd
Expose carry-out bits from WideCounter
2016-09-19 15:54:17 -07:00
Andrew Waterman
a49814c667
Allow WideCounter to not be reset
2016-09-18 18:45:51 -07:00
Andrew Waterman
5566bf1b13
Don't route PLIC interrupts through PRCI
...
The PLIC is local to the Coreplex, and PRCI should not be.
2016-09-14 11:01:05 -07:00
Howard Mao
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
Andrew Waterman
61cbe6164d
Add option to execute JAL from decode stage
...
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC. Caveat emptor.
2016-09-13 02:32:00 -07:00
Andrew Waterman
88440ebf89
Use PseudoLRU in BTB when possible (for powers of two)
2016-09-12 16:52:03 -07:00
Andrew Waterman
96185e4b16
tighten an assert condition
...
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
2016-09-12 16:49:46 -07:00
Andrew Waterman
beb141a20b
Allow M, A, D, C extensions to be disabled in misa register
2016-09-12 16:49:46 -07:00
Andrew Waterman
656aa78f7d
Pipeline FMAs more deeply by default
...
Rocket's QoR has improved enough that the FMAs are on the critical
path. This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
2016-09-09 11:06:42 -07:00
Andrew Waterman
eaa4b04ee5
Check D$ store->load collisions more precisely
...
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
2016-09-09 11:06:42 -07:00
Andrew Waterman
a7f47f3c23
Reduce default BTB size
...
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a
. The intent was to
fit the dhrystone working set (rofl) which the new value of 40 does.
2016-09-07 01:51:27 -07:00
Andrew Waterman
9fea4c83da
Add RV32F support
2016-09-07 00:05:39 -07:00
Andrew Waterman
66e9f027e0
Add MuxT to mux on Tuple2 and Tuple3
2016-09-07 00:05:38 -07:00
Andrew Waterman
511cc6c5c5
Evaluate arg to Boolean.option lazily
2016-09-07 00:05:38 -07:00
Andrew Waterman
a0dcd42e80
avoid erroneously setting tags valid during flush
2016-09-07 00:05:38 -07:00
Andrew Waterman
63679bb019
Add support for L1 data scratchpads instead of caches
...
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
Andrew Waterman
c05ba1e864
Add TileId parameter, generalizing GroundTestId
...
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
2016-09-02 00:10:50 -07:00
Howard Mao
c66318307c
no longer need to set invalidate_lr in RoCC examples
2016-08-31 22:05:35 -07:00
Howard Mao
27c674972c
tie off invalidate_lr in RoCC
2016-08-31 22:00:27 -07:00
Howard Mao
bb578494d8
don't override req.bits.phys in SimpleHellaCacheIF
2016-08-31 22:00:27 -07:00
Howard Mao
403cc1c5c4
fix DecoupledTLB to handle misses appropriately
2016-08-31 22:00:27 -07:00
Andrew Waterman
f4524e4c91
Add PML for Boolean.option; use it
2016-08-31 13:43:04 -07:00
Andrew Waterman
07d48df88a
Get rid of FPU RoCC port logic when RoCC not present
...
The previous approach used ex_reg_valid to determine whether to
source data from the FPU or RoCC. Thus, when the RoCC was not
present, it was still creating muxes. Using ex_cp_valid instead
gets rid of them.
2016-08-29 12:59:17 -07:00
Andrew Waterman
f91552a650
Add performance counter support
2016-08-29 12:31:52 -07:00
Andrew Waterman
1e3339e97c
Update breakpoints to match @timsifive's debug spec
2016-08-29 12:31:52 -07:00
Andrew Waterman
33eaf08b60
set missing port direction
...
Ideally, chisel should flag this as an error.
2016-08-29 12:31:52 -07:00
Ben Keller
79293f4fa2
Use a better iterator inside the DCache
2016-08-25 20:41:39 -07:00
Howard Mao
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00