Howard Mao
f0e9a2a081
Fix PutBlock after Release bug
...
There is logic in the broadcast hub to skip the outer acquire if there
is an outgoing release, since the data will be written out through the
release channel. However, this will cause an issue in the case of
PutBlock requests. If the tail beats of the PutBlock show up after the
outer release has already been sent, the data will be corrupted.
The fix is to make the outer release block if there are pending
inner PutBlock beats.
2016-10-28 18:26:34 -07:00
Andrew Waterman
e45b41b4b6
Don't rely on SeqMem output after read-enable is low
2016-10-27 23:44:10 -07:00
Howard Mao
900a7bbcf1
add PutAtomic support to width adapter
2016-10-26 09:58:26 -07:00
Wesley W. Terpstra
fee67c4abf
diplomacy: add methods to find {out,in}ner-most common node
2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
67ab27f5a5
diplomacy: guess the LazyModule name from the containing class
2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
4d50733548
tilelink2 ToAXI4: use helper method for a_last ( #418 )
2016-10-25 10:16:42 -07:00
Wesley W. Terpstra
a5ac106bb8
axi4 ToTL: fix decode error arbitration ( #417 )
...
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.
This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
2016-10-24 22:15:19 -07:00
Wesley W. Terpstra
4c815f7958
tilelink2 Parameters: fix {contains,supports}Safe ( #416 )
...
When there is only one manager, you still want to know if the address
was wrong on the link to that manager!
2016-10-24 20:37:04 -07:00
Wesley W. Terpstra
8bfd6bcd4d
axi4: ensure we accept AR before reporting R ( #411 )
2016-10-21 21:02:05 -07:00
Wesley W. Terpstra
7c334e3c34
axi4 ToTL: shorter critical path on Q.bits if errors go first
2016-10-17 01:00:49 -07:00
Wesley W. Terpstra
73010c79a3
axi4 ToTL: handle bad AXI addresses
2016-10-17 00:12:26 -07:00
Wesley W. Terpstra
501d6d689f
axi4: Test ToTL
2016-10-16 22:04:06 -07:00
Wesley W. Terpstra
5a1da63b5a
axi4: prototype ToTL adapter
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
72e5a97d40
tilelink2: factor out the OH1ToOH function
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
d09f43c32f
axi4 Bundles: add a size calculation helper
...
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
20288729b9
tilelink2 Isolation: cross the valid signals as well
...
Refactor the code to be less copy-pasty
2016-10-14 18:28:36 -07:00
Wesley W. Terpstra
ac0bb841da
AsyncQueue: cope with far reset propagation delay
2016-10-14 18:05:35 -07:00
Wesley W. Terpstra
8f3c2ddfc3
tilelink2 Crossing: these asserts should be done by the AsyncQueue
2016-10-14 16:54:09 -07:00
Wesley W. Terpstra
a82cfb8306
tilelink2: replace addr_hi with address ( #397 )
...
When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
2016-10-14 14:09:39 -07:00
Wesley W. Terpstra
54b73aef57
tilelink2: WidthWidget and Fragmenter no longer erase latency
2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
200cf3dd13
tilelink2 Nodes: include some options to test for conformance
2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
5d5b5a66f4
tilelink2 RAMModel: fix a write-bad-data bug
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e5a1483358
tilelink2 Fragmenter: eliminate most of the registers on A
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
99c7003d11
tilelink2: allow preemption of Fragmenter and WidthWidget
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b42cfdc9dd
tilelink2 Arbiter: there is only one winner
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b6e9b0c558
tilelink2 Arbiter: allow preemption of first beat
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0aebf9e341
tilelink2 ToAXI4: no arbitration path register needed
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0e897b905f
tilelink2 RegisterRouter: data path register is no longer required
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
c4eadd3ab3
tilelink2 Monitor: enforce stricter transaction ordering
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
d8a1163131
tilelink2 Monitor: don't enforce Irrevocable any more
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
405f66da32
tilelink2 WidthWidget: cope with Decoupled inputs
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e2e72ac979
tilelink2 Fragmenter: cope with Decoupled input
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
023c6402e9
tilelink2: switch to DecoupledIO syntax
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
4c1c52486b
axi4 Fragmenter: handle more inflight AXI requests than we have space
2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
8005266131
axi4 Fragmenter: refine sideband FSM for case of last fragment
2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
19064e602b
axi4 Fragmenter: align all output accesses
...
We promised the output is aligned. Make good on that!
2016-10-13 15:52:27 -07:00
Wesley W. Terpstra
84be93f9f3
axi4 Fragmenter: confirm correct handling of last
2016-10-13 14:01:23 -07:00
Wesley W. Terpstra
1c79a23a8b
axi4 Fragmenter: initialize error response to 0
2016-10-13 13:46:24 -07:00
Wesley W. Terpstra
958af132ba
axi4 Fragmenter: optimize dynamic slave lookup
2016-10-12 17:29:38 -07:00
Wesley W. Terpstra
11169d155c
axi4: add a Buffer to put between nodes
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a9a3f7dd4e
tilelink2 RAMModel: include name of test in output
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
345eefd81b
axi4: include unit tests
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a6c6d99848
axi4: prototype Fragmenter
2016-10-12 17:08:49 -07:00
Wesley W. Terpstra
c918aa6d89
axi4: name AdapterNode parameters properly
2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
a423f97844
axi4: parameterized AXI master constraint for aligned access
2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
673cf1fdb5
tilelink2 ToAXI4: must create irrevocable D for now
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
8e92ac32b7
tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
38b6c1c820
tilelink2 axi4: RegisterRouter can cut ready dependency
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
dc26736f32
axi4 tilelink2: include minAlignment and maxAddress in slaves
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
538437384a
tilelink2 Fragmenter: combine AccessAck errors
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
4caa543ad7
tilelink2: Fragmenter should not cut Acquire parameters
...
The correct response to misuse is to fail a requirement check.
Pretending that things are not caches could lead to inconsistency.
2016-10-11 22:38:03 -07:00
Wesley W. Terpstra
6336f94fa2
tilelink2: only caches can support B requests
2016-10-11 22:38:02 -07:00
Wesley W. Terpstra
4a975ca380
tilelink2: add a rightOR to go with our leftOR
2016-10-11 22:38:02 -07:00
Wesley W. Terpstra
b0e33f4a39
tilelink2: use TLArbiter in HintHandler
2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
683a2e6785
tilelink2: refactor firstlast helper method
2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
a404cd2abf
tilelink2: use NodeHandle to restore Crossing.node API
2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
876609eb0e
diplomacy: add NodeHandles to support abstraction
2016-10-10 13:15:25 -07:00
Wesley W. Terpstra
97af07eb3e
tilelink2: clarify use of Isolation
2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
b5f5ef69c1
regmapper: eliminate race condition in RegisterCrossing bypass
2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
f250426728
tilelink2: blow up if the channels carry data when they should not
2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
6d6aa3eb13
tilelink2: Isolation must also connect reset_n
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
cb7b16f1a9
util: exchange resets between AsyncQueue source and sink
2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
adf5f1807b
tilelink2: ToAXI4 bridge added
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
e856cbe3a6
axi4: SRAM for testing
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
abb02aa6f4
axi4: add a RegisterRouter for generic devices
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
2f7081aeaf
tilelink2: make mask generation reusable
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
b29d34038e
axi4: diplomacy capable AXI4
2016-10-10 11:21:50 -07:00
Henry Cook
1e69a2dc1c
[tilelink2] allow TL monitors to be globally enabled or disabled ( #392 )
2016-10-09 12:34:10 -07:00
Wesley W. Terpstra
e5ac0f717f
tilelink2: split isolation gates by direction
2016-10-07 12:03:43 -07:00
Albert Ou
ad618fd55d
plic: Fix bit extraction
2016-10-06 18:05:03 -07:00
Andrew Waterman
b1c777c7a2
Fix PLIC enable bit access for #ints >= tlDataBits
2016-10-06 16:21:14 -07:00
Jacob Chang
fe641c14a1
tilelink2: Add support for different noise generator in fuzzer ( #386 )
2016-10-06 13:20:13 -07:00
Andrew Waterman
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
Wesley W. Terpstra
6ec2e7c5bd
tilelink2: Legacy should preserve the access size ( #378 )
...
* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
2016-10-03 17:25:31 -07:00
Wesley W. Terpstra
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
c85e42a303
tilelink2: Nodes should accept full PortParameters
...
We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
2016-10-03 16:09:49 -07:00
Wesley W. Terpstra
f2ca2178bf
graphML: CTO's like colour
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
fe0875b084
LazyModule: output final verilog Module name
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
52c1a053ff
tilelink2 RegisterRouter: test fully Decoupled behaviour
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
422e6357a4
tilelink2 RegisterCrossing: Queues go from RV to Irrevocable
...
AsyncQueue is still a Queue.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
02f89fb530
RegMapper: clarify interface is DecoupledIO
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
8a268268ad
tilelink2 RegField: clarify restrictions on functions
...
RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
bff0ffa428
tilelink2 RegisterRouter: fix output data glitches
...
If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
2016-10-02 02:24:02 -07:00
Megan Wachs
28eba9b5ac
clint/plic: Move the default addresses
2016-10-01 15:46:55 -07:00
mwachs5
9a381e88d1
Suggest sane names for common objects ( #369 )
...
* Suggest sane names for common objects frequently instantiated with factory methods
* Suggest names for common primitives using more Scala-esque Options
2016-09-30 16:19:25 -07:00
Wesley W. Terpstra
0ebab0976a
tilelink2 Isolation: add enable signal ( #368 )
2016-09-30 04:54:40 -07:00
Wesley W. Terpstra
d3547a6193
tilelink2: Isolation gate insertion module
2016-09-30 01:50:33 -07:00
Wesley W. Terpstra
9b0654be52
tilelink2 Crossing: helpful constructor objects
2016-09-30 01:48:47 -07:00
Wesley W. Terpstra
80f7bb49e3
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Wesley W. Terpstra
6d8c965f04
tilelink2 Crossing: cut the crossing between clock domains
2016-09-29 17:35:10 -07:00
Wesley W. Terpstra
20f42a8762
tilelink2: reuse the halves of the AsyncQueue
2016-09-29 17:35:08 -07:00
Wesley W. Terpstra
8e4c1e567c
tilelink2: add types for a TL clockless interface
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
02ce8c2ca4
tilelink2 Nodes: rename RootNode => BaseNode
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
754fcf9831
tilelink2: rename BaseNode to SimpleNode
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
cfdb8ca797
tilelink2 LazyModule: remove obsolete connect method
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
f2e438833c
tilelink2 Nodes: generalize a node into inner and outer halves
...
This lets us create nodes which transform from one bus to another.
2016-09-29 17:33:11 -07:00
Andrew Waterman
2bdf8c2be7
Merge branch 'master' into move-to-util
2016-09-29 14:42:11 -07:00
Howard Mao
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Megan Wachs
45bd63fcc6
jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec
2016-09-29 13:49:14 -07:00
Henry Cook
32f3f94882
[tilelink2] Fix zero-width wires in RAMModel.
2016-09-28 18:02:04 -07:00
Henry Cook
69e121260e
[tilelink2] Add unit tests for many TL2 components
...
These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
2016-09-28 18:02:04 -07:00
Henry Cook
81123f84c9
[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. ( #356 )
2016-09-27 18:06:21 -07:00
mwachs5
f9e0a7ac24
Merge branch 'master' into async_register_crossing
2016-09-27 15:54:34 -07:00
Wesley W. Terpstra
eaea138d0d
tilelink2: don't use chisel3 namespace ( #355 )
2016-09-27 14:44:26 -07:00
Henry Cook
f5502df6ab
Merge branch 'master' into async_register_crossing
2016-09-27 14:08:27 -07:00
Wesley W. Terpstra
357d06ac9c
tilelink2 WidthWidget: Gets must have their mask adjusted ( #353 )
...
The mask of a Get should also be converted.
This manifested as a bug when going from 32=>64 bits. A large Get
could end up with mask that was not full.
2016-09-27 14:06:02 -07:00
Megan Wachs
3ce08f40a5
crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations
2016-09-27 13:36:28 -07:00
Howard Mao
ea9f0a868f
TileLink utility objects should not take implicit parameters
...
We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
2016-09-26 17:28:21 -07:00
Wesley W. Terpstra
d9e209365d
Tl2 addr width0 ( #346 )
...
* tilelink2 Edges: add accessor methods for address and addr_{hi,lo}
* tilelink2: use addr_lo instead of relying on truncation
Truncation can mess up if the width should be 0, but IS 1.
2016-09-26 17:00:03 -07:00
Wesley W. Terpstra
72c205b54f
tilelink2 AddressSet: add .misaligned(low, size) helper method ( #345 )
...
This helps devices with misaligned ranges still connect to TL2.
2016-09-26 16:01:09 -07:00
Wesley W. Terpstra
1773eb4405
tilelink2 LazyModule: output GraphML of the bus
2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
35da9320bc
tilelink2 Nodes: expose connectivity in RootNode
2016-09-26 14:35:46 -07:00
mwachs5
77a0f76289
Cleanup jtag dtm ( #342 )
...
* debug: Clean up Debug TransportModule synchronizer
With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.
I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
2016-09-26 11:10:27 -07:00
Wesley W. Terpstra
d787bae0d0
tilelink2 Xbar: decouple ready from valid ( #338 )
...
This moves the Xbar from using custom code to using the Arbiter.
The arbiter has better ready-valid decoupling.
2016-09-23 16:24:29 -07:00
Wesley W. Terpstra
d175bb314d
Periphery: make bus width and arithmetic atomics configurable ( #337 )
2016-09-23 15:25:58 -07:00
Wesley W. Terpstra
47843d8ec1
tilelink2: maxLgSize should be accurate ( #332 )
2016-09-22 22:06:22 -07:00
Wesley W. Terpstra
c5706afc11
RegField: remove obsolete split method
...
This is now natively supported by the regmap(...) invocation.
2016-09-22 20:52:47 -07:00
Wesley W. Terpstra
fc44151f10
RegField: add name and description fields
...
In the future we can generate interesting documentation and headers.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
5e34b313ee
RegMapper: regmap(...) now takes BYTE addresses
...
If a device has configurable bus-width, we need a stable way of
enumerating registers. The byte offset stays unchanged.
This change also makes it possible to put an arbitrary number of RegFields
starting at some address which are then chopped up into appropriately bus-
sized registers.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
972ca06729
RegField: remove RegField.bytes; it was dangerous
...
The implementation unconditionally drove the register.
This made it incompatible with drivers from the device itself.
Besides, writing only parts of a register at a time is ultra-shady.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
a421469754
tilelink2: change adapters to use TLAdapter(params, defaults)(node)
...
This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.
For example, this:
peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
2016-09-22 20:52:46 -07:00
Henry Cook
391be8d740
tilelink2 RegisterRouter: minLatency is never more than 1
2016-09-22 15:51:15 -07:00
Wesley W. Terpstra
a3e88fa13a
tilelink2 Atomics: optimize the sign-extension circuit
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ed038678ef
tilelink2 Fuzzer: work around for firrtl/verilator performance issue
...
Big Vec()s cause very slow compilation.
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
1e7480b6fc
tilelink2 Monitor: work around for firrtl/verilator performance issue
...
Big Vec()s cause problems for these tools.
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ec2030df31
tilelink2 Legacy: convert TL1 atomic operand size
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e5da3eb8bb
tilelink2 Atomics: support arithmetic atomics
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
5b80fe5b51
tilelink2 Atomics: support Logical AMOs
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
4066fbe18f
tilelink2 RAMModel: exploit latency to remove bypass
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e0ade8c5a9
tilelink2 Atomics: exploit minLatency to eliminate bypass
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
3bb2580223
tilelink2 Monitor: detect minLatency violations
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
2b24c4b1b4
tilelink2: most adapters can wipe away latency
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
c115913624
tilelink2 Buffer: increase the minLatency on ports
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
05beb20dc4
tilelink2: specify the minLatency for SRAM+RR
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
44277c1db3
tilelink2 Parameters: include a minLatency parameter for optimization
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
cf39c32b0e
tilelink2 Fuzzer: test Atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
2b9403633d
tilelink2 RAMModel: support (by ignoring) atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
ce204f604a
tilelink2 AtomicAutomata: prototype flow control complete
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
42b10356fa
tilelink2: add a general-purpose Arbiter
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
7636e772c8
tilelink2 Fuzzer: only generate legal atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
f5d604d8f8
tilelink2 Parameters: poison ports with unsafe atomics
...
We need to detect if an AtomicAutomata's output ever gets mixed
with some other source of operations.
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
d1151e2f0f
tilelink2 Nodes: split connect into eager and lazy halves
2016-09-22 15:18:50 -07:00
Wesley W. Terpstra
684072023f
tilelink2 Monitor: make it a LazyModule in the hierarchy
2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
def497861b
tilelink2 Bundles: add 1-way snoop bundles
2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
69a1f8cd1f
tilelink2 Monitor: detect if sources are mishandled
2016-09-22 15:14:19 -07:00
Albert Ou
d76b762657
tilelink2 Fragmenter: Mask low bits of D channel addr_lo
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This fixes an issue where passing addr_lo through unchanged triggered
unaligned address assertions in the Monitor.
2016-09-22 12:36:28 -07:00
Howard Mao
cd96a66ba6
replace verilog clock divider with one written in Chisel
2016-09-22 11:32:29 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Henry Cook
335e866176
[unittest] Parallelize UnitTestSuite ( #319 )
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* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.
* [util] Timer spacing cleanup
* [unittest] Remove Config reference to UnitTestTimeout
2016-09-21 13:05:22 -07:00