39ec927a3f
replace complicated pattern substitutions with automatic variable
2016-06-28 18:30:11 -07:00
a39a0c0ec4
.prm is output of chisel stage, not firrtl stage
2016-06-28 17:34:37 -07:00
b30e0254ee
fix Makefrag to detect all Chisel source files
2016-06-28 16:39:10 -07:00
ebef4ddad0
remove mention of HTIF from README
2016-06-28 15:23:32 -07:00
f1cbb2ff77
Turn up optimization for Verilator compilation
2016-06-28 14:12:46 -07:00
74cd588c65
refactor uncore to split into separate packages
2016-06-28 14:10:25 -07:00
a9e0a5e2df
changes to imports after uncore refactor
2016-06-28 14:09:31 -07:00
80670c08d7
changes to imports after uncore refactor
2016-06-28 13:15:56 -07:00
9feca99d5d
make PutBlock wmask argument match Put
2016-06-28 13:10:46 -07:00
b936aa9826
refactor uncore files into separate packages
2016-06-28 13:10:46 -07:00
c10691b616
Don't take interrupts on instructions in branch shadow
...
In situations like
j 1f
nop
1: nop
the interrupt could be taken on the first nop.
2016-06-28 12:47:49 -07:00
a70dee17ea
Make RoCC energy-saving logic mirror same for D$
2016-06-28 12:47:45 -07:00
c725a78086
Merge RTC into PRCI
2016-06-27 23:08:29 -07:00
97e74aec3a
Merge RTC and PRCI
2016-06-27 23:06:07 -07:00
d10fc84a8b
no longer require caching interfaces for groundtest tiles
2016-06-27 17:32:49 -07:00
f438e7048c
no longer need DummyCache since tiles no longer require cached interface
2016-06-27 16:32:06 -07:00
ec5b9dfc86
make sure trackers can handle case where there are no caching clients
2016-06-27 16:29:51 -07:00
2dd8d90ae4
make Comparator fit the GroundTest model
2016-06-27 16:01:32 -07:00
7fea376f8c
make comparator fit into GroundTest interface
2016-06-27 16:00:24 -07:00
a93a70c8ec
make sure merged voluntary releases are handled properly
2016-06-27 11:40:32 -07:00
3d63329b42
get rid of incorrect, broken, or useless configs in README
2016-06-24 15:37:56 -07:00
800e62412a
use the fast version of asm/bmark-tests
2016-06-24 15:36:10 -07:00
d6ba0437ff
merge different configs into regression suites to reduce travis build times
2016-06-24 13:02:29 -07:00
87a4858aa6
Exit from testbench, not C code
...
Otherwise, we don't get coverage data from the simulator.
2016-06-23 20:54:07 -07:00
4cd709c516
fix Comparator in groundtest
2016-06-23 15:47:24 -07:00
238ce99f5c
fix requirement in Comparator
2016-06-23 15:47:09 -07:00
568bfa6c50
Purge legacy HTIF things
...
The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
6fb07b1b79
Remove legacy HTIF things
2016-06-23 13:19:31 -07:00
6f85056494
Remove reliance on HtifKey
2016-06-23 13:18:51 -07:00
354b81c8fe
Remove legacy HTIF things
...
The SCR file is gone, too, because it is tightly coupled. The
general concept could be revived as a module that somehow connects
to (or is contained by) the debug module.
2016-06-23 13:17:11 -07:00
2d44be747a
Fix groundtest without HTIF
2016-06-23 12:17:26 -07:00
1844bac5bc
Use stop() to exit cleanly
2016-06-23 12:16:37 -07:00
30331fcaeb
Remove HTIF; use debug module for testing in simulation
2016-06-23 00:32:05 -07:00
f57524e0c1
Remove FENCE.I from debug ROM; specialize for RV64
2016-06-23 00:01:26 -07:00
6d43c0a945
Mask interrupts during single-step
2016-06-23 00:01:06 -07:00
5644a2703a
Avoid need for FENCE.I in debug programs
...
This is a hack to work around caching the (uncacheable) debug RAM. The
RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR.
2016-06-23 00:01:06 -07:00
7f88a00a38
Always verify BTB result; don't bother flushing it
...
This improves CPI for things like
lbu t0, (t0)
j foo
addi t0, t0, 1
where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
2016-06-23 00:01:06 -07:00
255ef05e21
bump rocket
2016-06-22 17:59:05 -07:00
338f959620
get rid of commented out code
2016-06-22 17:36:53 -07:00
4fbe7d6cf7
split the isa tests properly
2016-06-22 16:14:02 -07:00
4c31248917
make sure UseAtomics is on when PTW is being used
2016-06-22 16:09:45 -07:00
5edb448a1f
get rid of slow DualCoreConfig in Travis for now
2016-06-22 16:09:14 -07:00
3c973d429a
rename SmallConfig to WithSmallCores
2016-06-22 16:08:27 -07:00
9b9ddd0d54
get rid of leftover backup memory code
2016-06-22 16:06:41 -07:00
e3d3b2264a
fix MuxCase and MuxLookup
2016-06-21 14:03:10 -07:00
0967f3cfed
use MuxCase and MuxLookup instead of MuxBundle
2016-06-21 14:01:23 -07:00
e3391b36b2
get rid of MuxBundle now that MuxCase and MuxLookup are fixed
2016-06-21 10:43:44 -07:00
ff43238e6e
give DualCoreConfig L2 cache to speed up test runs
2016-06-20 17:58:26 -07:00
daa0f3038f
invoke firrtl jar directly in order to control heap memory usage
2016-06-20 13:02:31 -07:00
82169e971e
Dynamically compute number of L1 client channels
...
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.
This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
2016-06-20 13:02:31 -07:00
