Megan Wachs
665c2a349c
Correct Debug + WFI Interactions
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1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
2017-06-27 13:42:38 -07:00
Zihao Yu
c9cfe46604
rocket,Rocket: fix type mismatch ( #819 )
2017-06-27 11:22:08 -07:00
Jack Koenig
8d07d0af38
Merge pull request #820 from freechipsproject/bump-firrtl
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Bump firrtl to get constant propagation improvements
2017-06-26 18:47:50 -07:00
Wesley W. Terpstra
66f64a9759
tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters ( #822 )
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idCount <= 1 implies that no more than one transaction can be inflight,
so there is no need to interlock R+W. However, when stripBits > 0, it is
possible for a non-FIFO master to have > 1 idCount. In this case, we
also don't need to interlock R+W.
2017-06-26 17:54:17 -07:00
Jack
e461e0f796
Bump firrtl to get constant propagation improvements
2017-06-26 17:18:52 -07:00
Andrew Waterman
72c46e6c05
Merge pull request #818 from sashimi-yzh/faster-verilator-compile
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emulator,Makefile-verilator: add --output-split-cfuncs flag
2017-06-26 11:39:42 -07:00
Zihao Yu
fc85a3ce02
emulator,Makefile-verilator: add --output-split-cfuncs flag
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* Originally verilator will generate a large cpp file containing a large
function, which costs about 13 min to compile. By using --output-split-cfuncs,
this large function will be splitted into several functions in servral
files. This will greatly improve the compile time with 'make -j'. By '-j32',
the compile time can be reduced to about 1 min.
2017-06-26 14:29:29 +08:00
Wesley W. Terpstra
7a0655ae88
Merge pull request #816 from freechipsproject/reduce-axi-queues
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Reduce AXI4 queues
2017-06-23 18:31:41 -07:00
Wesley W. Terpstra
8ca6c10994
tilelink2: ToAXI4 can strip off low source ID bits
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Some TL converters place extra meta data in the low bits of source.
Examples include the TLFragmenter and CacheCork.
This new argument makes it possible to save AXI4 ID space by reclaiming
those bits upon conversion.
2017-06-23 17:22:45 -07:00
Wesley W. Terpstra
feecfb53ed
axi4: Deinterleaver need not make a Q for an unused AXI id
2017-06-23 17:22:42 -07:00
Wesley W. Terpstra
9bea7c1c58
Merge pull request #815 from freechipsproject/reduce-others
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Reduce others
2017-06-23 12:13:48 -07:00
Wesley W. Terpstra
2d8b2f4edd
ReduceOthers: remove constants from the balanced AND tree
2017-06-23 00:28:05 -07:00
Henry Cook
ad4b454b49
isp: passthru based on edgesOut = edgesIn ( #814 )
2017-06-22 21:23:49 -07:00
Wesley W. Terpstra
48611266fa
diplomacy: use ReduceOthers in the RegMapper
2017-06-22 19:43:47 -07:00
Wesley W. Terpstra
11d1cb02eb
util ReduceOthers produces nlogn cost ready-valid logic
2017-06-22 19:43:20 -07:00
Scott Johnson
1f18a37f01
Merge pull request #813 from freechipsproject/scottj97-patch-1
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Update Readme: rocket-chip uses Travis, not Jenkins
2017-06-22 13:33:15 -07:00
Jack Koenig
1f137cb9ff
Merge pull request #800 from ss2783/patch-1
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GeneratorUtils: support to elaborate a RawModule
2017-06-22 12:34:41 -07:00
Colin Schmidt
aced18b3bb
Move RoCC interface to Diplomacy and TL2 ( #807 )
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* Move RoCC interface to Diplomacy and TL2
* guard rocc arbiter to prevent zero-width wires
2017-06-22 12:07:09 -07:00
Scott Johnson
bd803d278a
Update Readme: rocket-chip uses Travis, not Jenkins
2017-06-22 10:16:10 -07:00
Scott Johnson
f1130b2faf
Merge pull request #812 from freechipsproject/bump-tools
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Bump riscv-tools to get new riscv-isa-sim
2017-06-22 08:40:00 -07:00
Scott Johnson
a7273bccbe
Bump riscv-tools to get new riscv-isa-sim
2017-06-21 22:34:25 -07:00
Henry Cook
0fdaa28694
Merge pull request #811 from freechipsproject/isp-tweaks
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Assorted changes based on ISP use cases
2017-06-20 19:24:28 -07:00
Henry Cook
bf431c0a53
groundtest: fix test ram width
2017-06-20 18:11:22 -07:00
Wesley W. Terpstra
2f2fe0a973
clint: don't ask for what you know (nTiles)
2017-06-20 17:21:53 -07:00
Henry Cook
1c97a2a94c
allow re-positionable PLIC and Clint, and change coreplex internal network names
2017-06-20 17:18:45 -07:00
Henry Cook
5552f23294
tims: explictly name them for generated address map
2017-06-20 17:18:29 -07:00
Henry Cook
6b79842e66
dcache: just left shift by untagbits to get tag
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Always safe because of the requirement on coreplex/RocketTiles.scala:126
2017-06-20 16:35:28 -07:00
Henry Cook
7521050a48
Merge pull request #810 from freechipsproject/isp-fixes
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ISP fixes
2017-06-20 16:35:06 -07:00
Wesley W. Terpstra
bb309e573f
TLSplitter: special-case the case of no split necessary
2017-06-20 14:10:25 -07:00
Wesley W. Terpstra
53f030c037
TLSplitter: default policy is roundRobin
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Track commit 274d908d98
2017-06-20 14:03:01 -07:00
Wesley W. Terpstra
1aa4f5ce33
TLSplitter: QoR improvements
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Track commit 985d9750e6
2017-06-20 14:01:07 -07:00
Wesley W. Terpstra
f6e0dd12c8
TLSplitter: ManagerUnification is not used in Xbars
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Track the change made in 5994714970
2017-06-20 13:58:30 -07:00
Andrew Waterman
f396b4142d
Merge pull request #806 from freechipsproject/mulh
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Improve integer mul/div
2017-06-20 13:01:16 -07:00
Colin Schmidt
675f183dd2
refactor ICache to be reusable by other frontends ( #808 )
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* refactor ICache to be reusable by other frontends
specifically one that would like to change the fetch width and number of
bytes in an instruction
2017-06-20 08:21:01 -07:00
Andrew Waterman
a6d9884cc0
Improve integer mul/div
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- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
2017-06-19 12:09:21 -07:00
Shreesha Srinath
ff1f0170dc
changing SystemVerilog params to Verilog style ( #801 )
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vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
2017-06-16 22:47:12 -07:00
Richard Xia
31415060fe
Merge pull request #802 from freechipsproject/fix-decode-of-instruction-after-ebreak
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Check for rvc before declaring illegal instruction after an ebreak.
2017-06-16 15:07:24 -07:00
Richard Xia
61c39da475
Check for rvc before declaring illegal instruction after an ebreak.
2017-06-16 10:49:36 -07:00
Megan Wachs
d0f8cdd00c
Merge pull request #804 from freechipsproject/travis_cache_stages
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travis: attempt to make 2 build stages for cache
2017-06-16 07:31:56 -07:00
Wesley W. Terpstra
a89c0551b7
travis: use travis_wait again
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Timeouts due to inactivity again :-/
2017-06-15 23:04:17 -07:00
Megan Wachs
30a3e3ef55
travis: attempt to make 2 build stages for cache
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First stage builds riscv-tools, next stage builds verilator
2017-06-15 21:31:15 -07:00
Wesley W. Terpstra
93d423d202
diplomacy: optimize IdRange.contains ( #798 )
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This should make an optimal circuit for a wider class of ranges.
2017-06-15 15:56:14 -07:00
Shreesha Srinath
4059d9417f
GeneratorUtils: support to elaborate a RawModule
2017-06-15 14:33:02 -07:00
Megan Wachs
d316aeb275
Merge pull request #799 from freechipsproject/bump-riscv-tools-start-multiple-harts
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Bump riscv-tools to pick up FESVR which allows starting all harts
2017-06-15 13:55:46 -07:00
Henry Cook
5368ea60fe
Merge pull request #757 from freechipsproject/isp-port
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Inter-System-Port
2017-06-15 13:07:19 -07:00
Megan Wachs
9a789fc0cf
Bump riscv-tools to pick up FESVR which allows starting all harts
2017-06-15 11:05:07 -07:00
Jack Koenig
2665a3eb2f
Bump firrtl ( #797 )
2017-06-15 10:06:24 -07:00
Wesley W. Terpstra
c259e39fa3
Merge pull request #796 from freechipsproject/buffer-instance
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diplomacy: BufferParams can now directly create a Queue
2017-06-14 15:58:29 -07:00
Wesley W. Terpstra
1f8c4ba4ca
CoreplexNetwork: don't force a buffer on the coherence manager
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Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
2017-06-14 14:27:23 -07:00
Wesley W. Terpstra
4a15d47061
diplomacy: BufferParams can now directly create a Queue
2017-06-14 13:47:37 -07:00