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Commit Graph

52 Commits

Author SHA1 Message Date
Andrew Waterman
a3358f34a0 Fix priority inversion for two back-to-back divides (#948)
If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit.  While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
2017-08-10 17:12:09 -07:00
Andrew Waterman
e140893a01 Use 1-entry queue on processor-side E-channel
The cache can't sink a grant every cycle, so extra E buffering doesn't help.
2017-07-31 18:06:54 -07:00
Yunsup Lee
f473e6bad0 tile: add optional boundary buffers 2017-07-31 15:57:22 -07:00
Wesley W. Terpstra
eadf4e9fcc Revert "tile: add option for tile boundary buffers"
This reverts commit b64b87ad07.

The crossings already have buffering in those places where it was
appropriate. Adding more does not help flow through paths.
2017-07-29 00:03:24 -07:00
Henry Cook
7eeb9dfd88 Merge pull request #899 from freechipsproject/wrapper-dedup
Stabilize tile wrappers for downstream tools
2017-07-28 10:52:59 -07:00
Henry Cook
b64b87ad07 tile: add option for tile boundary buffers 2017-07-27 17:30:51 -07:00
Henry Cook
266ed56e8d tile: turn off more slave port monitors 2017-07-27 15:28:53 -07:00
Andrew Waterman
15878d4691 Perform some control-flow transfers within the Frontend 2017-07-25 15:19:16 -07:00
Henry Cook
01ca3efc2b Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
Henry Cook
4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845)
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
2017-07-07 10:48:16 -07:00
Andrew Waterman
90a7d6a343 Add L2 TLB option 2017-07-06 01:19:18 -07:00
Colin Schmidt
aced18b3bb Move RoCC interface to Diplomacy and TL2 (#807)
* Move RoCC interface to Diplomacy and TL2

* guard rocc arbiter to prevent zero-width wires
2017-06-22 12:07:09 -07:00
Andrew Waterman
76af15a6ff Fix FPU control bug for div/sqrt
I was examining a WB-stage control signal instead of a MEM-stage control
signal.  I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
2017-06-09 15:51:06 -07:00
Andrew Waterman
5a4daebbcc minNum -> minimumNumber (#766) 2017-06-08 11:12:52 -07:00
Andrew Waterman
8cb250cfe6 Fix FMUL sign, again (#789) 2017-06-08 01:50:00 -07:00
Andrew Waterman
07ad9203ff Fix FMUL sign of zero 2017-06-05 17:35:42 -07:00
Andrew Waterman
8229bdee03 Remove FP unboxing from FMA critical path 2017-06-02 20:44:52 -07:00
Andrew Waterman
7504b47bbe Improve code quality in FP->FP and Int->FP units 2017-06-02 20:44:52 -07:00
Andrew Waterman
84c4ae775f Improve QoR for FP->Int conversions 2017-06-02 20:44:52 -07:00
Andrew Waterman
07968df183 Refactor FP Classify 2017-06-02 20:44:52 -07:00
Andrew Waterman
6ecd58a977 Incorporate new div/sqrt unit 2017-06-02 20:44:15 -07:00
Andrew Waterman
b2b4c1abcd Separate tag ECC and data ECC options (#761) 2017-05-23 12:51:48 -07:00
Henry Cook
5f22e91a7f rocc: fix RoccExampleConfig 2017-05-16 16:44:53 -07:00
Henry Cook
a19fc2549e tile: add tileBus xbar 2017-05-16 16:12:01 -07:00
Megan Wachs
922a8ef5e0 local_interrupts: Correct off-by-1 if there is no SEIP 2017-05-02 21:55:25 -07:00
Andrew Waterman
3a1a37d41b Support PutPartial in ScratchpadSlavePort 2017-05-02 03:07:02 -07:00
Megan Wachs
d67738204f Interrupts: Less Pessimistic Synchronization (#714)
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
2017-04-28 14:49:24 -07:00
Andrew Waterman
7416f2a17e Unbreak groundtest 2017-04-28 02:10:33 -07:00
Henry Cook
3d0ed80ef6 new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels 2017-04-27 18:17:31 -07:00
Andrew Waterman
e23ee274f6 Size hartid field with NTiles, not XLen 2017-04-26 20:11:43 -07:00
Wesley W. Terpstra
11ff4dfbb9 rocket: seip (int 9) is only present if VM is enabled (#699) 2017-04-24 15:58:33 -07:00
Andrew Waterman
3b2c15b648 Use tininess-after-rounding in FPU 2017-04-24 02:01:15 -07:00
Andrew Waterman
34d45b4fb0 Fix whitespace error 2017-04-14 01:03:11 -07:00
Andrew Waterman
9a983c12a3 Implement new FP encoding proposal
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
2017-04-10 22:38:25 -07:00
Andrew Waterman
70e7e90c02 Remove splitMetadata option from L1 caches
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
2017-03-30 15:48:55 -07:00
Andrew Waterman
80fb002962 Don't use Vec as lvalue 2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
Andrew Waterman
c7c357e716 Add local interrupts to core (but not yet to coreplex) 2017-03-27 16:37:09 -07:00
Andrew Waterman
0e2b780089 Bump hardfloat, giving us the 5th rounding mode finally! 2017-03-26 14:20:16 -07:00
Andrew Waterman
e710e32f10 Implement new FP encoding proposal
Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
2017-03-26 14:20:16 -07:00
Andrew Waterman
bb42f3bf3b WIP on FPU subword recoding 2017-03-26 14:20:16 -07:00
Henry Cook
996a31364a rocket: remove hard-coded paddrBits (#610)
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
Andrew Waterman
0380aed329 PUM -> SUM 2017-03-24 16:39:52 -07:00
Andrew Waterman
aace526857 WIP on PMP 2017-03-24 16:39:52 -07:00
Andrew Waterman
24a2278fc4 Perform all illegal-instruction detection in ID stage
This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
2017-03-09 11:29:51 -08:00
Andrew Waterman
db0a02b78e WIP on priv-1.10 2017-03-09 11:29:51 -08:00
Andrew Waterman
603b8af2eb Don't canonicalize 32-bit FP results in the various pipelines
It's redundant with the new scheme, so just adds HW for no reason.
2017-03-07 20:51:32 -08:00
Andrew Waterman
f505aba1ac Use sNaN value for flw, like other single-precision ops 2017-03-07 20:51:32 -08:00
Andrew Waterman
cc389bea90 Fix in-register representation of fdiv.s/fsqrt.s result
We were zero-extending it, which is a double-precision zero in the recoded
format.  So, when spilled and reloaded with fsd/fld, the original value
was destroyed.  Instead, set the MSBs so that it represents sNaN.  When
spilled, the single-precision number will be preserved as the NaN payload.
2017-03-07 20:51:32 -08:00
Henry Cook
d0ae087587 rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00