riscv/rocket-chip
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996a31364a
rocket-chip/src/main/scala/tile
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Henry Cook 996a31364a rocket: remove hard-coded paddrBits (#610) 
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
..
BaseTile.scala rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00
Core.scala rocket: remove hard-coded paddrBits (#610) 2017-03-24 22:30:18 -07:00
FPU.scala Perform all illegal-instruction detection in ID stage 2017-03-09 11:29:51 -08:00
Interrupts.scala Heterogeneous Tiles (#550) 2017-02-09 13:59:09 -08:00
L1Cache.scala rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00
LegacyRoCC.scala PUM -> SUM 2017-03-24 16:39:52 -07:00
Package.scala Heterogeneous Tiles (#550) 2017-02-09 13:59:09 -08:00