Andrew Waterman
e6c1bcfedd
Expose carry-out bits from WideCounter
2016-09-19 15:54:17 -07:00
Andrew Waterman
a49814c667
Allow WideCounter to not be reset
2016-09-18 18:45:51 -07:00
Andrew Waterman
5566bf1b13
Don't route PLIC interrupts through PRCI
...
The PLIC is local to the Coreplex, and PRCI should not be.
2016-09-14 11:01:05 -07:00
Howard Mao
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
Andrew Waterman
61cbe6164d
Add option to execute JAL from decode stage
...
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC. Caveat emptor.
2016-09-13 02:32:00 -07:00
Andrew Waterman
88440ebf89
Use PseudoLRU in BTB when possible (for powers of two)
2016-09-12 16:52:03 -07:00
Andrew Waterman
96185e4b16
tighten an assert condition
...
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
2016-09-12 16:49:46 -07:00
Andrew Waterman
beb141a20b
Allow M, A, D, C extensions to be disabled in misa register
2016-09-12 16:49:46 -07:00
Andrew Waterman
656aa78f7d
Pipeline FMAs more deeply by default
...
Rocket's QoR has improved enough that the FMAs are on the critical
path. This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
2016-09-09 11:06:42 -07:00
Andrew Waterman
eaa4b04ee5
Check D$ store->load collisions more precisely
...
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
2016-09-09 11:06:42 -07:00
Andrew Waterman
a7f47f3c23
Reduce default BTB size
...
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a
2016-09-07 01:51:27 -07:00
Andrew Waterman
9fea4c83da
Add RV32F support
2016-09-07 00:05:39 -07:00
Andrew Waterman
66e9f027e0
Add MuxT to mux on Tuple2 and Tuple3
2016-09-07 00:05:38 -07:00
Andrew Waterman
511cc6c5c5
Evaluate arg to Boolean.option lazily
2016-09-07 00:05:38 -07:00
Andrew Waterman
a0dcd42e80
avoid erroneously setting tags valid during flush
2016-09-07 00:05:38 -07:00
Andrew Waterman
63679bb019
Add support for L1 data scratchpads instead of caches
...
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
Andrew Waterman
c05ba1e864
Add TileId parameter, generalizing GroundTestId
...
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
2016-09-02 00:10:50 -07:00
Howard Mao
c66318307c
no longer need to set invalidate_lr in RoCC examples
2016-08-31 22:05:35 -07:00
Howard Mao
27c674972c
tie off invalidate_lr in RoCC
2016-08-31 22:00:27 -07:00
Howard Mao
bb578494d8
don't override req.bits.phys in SimpleHellaCacheIF
2016-08-31 22:00:27 -07:00
Howard Mao
403cc1c5c4
fix DecoupledTLB to handle misses appropriately
2016-08-31 22:00:27 -07:00
Andrew Waterman
f4524e4c91
Add PML for Boolean.option; use it
2016-08-31 13:43:04 -07:00
Andrew Waterman
07d48df88a
Get rid of FPU RoCC port logic when RoCC not present
...
The previous approach used ex_reg_valid to determine whether to
source data from the FPU or RoCC. Thus, when the RoCC was not
present, it was still creating muxes. Using ex_cp_valid instead
gets rid of them.
2016-08-29 12:59:17 -07:00
Andrew Waterman
f91552a650
Add performance counter support
2016-08-29 12:31:52 -07:00
Andrew Waterman
1e3339e97c
Update breakpoints to match @timsifive's debug spec
2016-08-29 12:31:52 -07:00
Andrew Waterman
33eaf08b60
set missing port direction
...
Ideally, chisel should flag this as an error.
2016-08-29 12:31:52 -07:00
Ben Keller
79293f4fa2
Use a better iterator inside the DCache
2016-08-25 20:41:39 -07:00
Howard Mao
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
